SFF-8436 QSFP+ 10Gbs 4X Pluggable Transceiver协议参考

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"SFF-8436 QSFP+ 10Gbs 4X Pluggable Transceiver" 是一份由 SFF（Small Form-factor Pluggable）委员会发布的文档，专门针对10吉比特每秒（10Gbps）的四通道QSFP+（Quadruple Small Form-factor Pluggable Plus）可插拔传输器进行详细规范。该标准修订至第4.1版，发布日期为2011年8月24日。这份文档对于系统制造商、系统集成商以及硬盘驱动器供应商来说具有重要意义，因为它定义了插件式四通道QSFP+模块、直连电缆插头和连接器的电气、光学和机械特性。 SFF-8436标准不仅包含了数据速率的提升，从INF-8438标准中增加了对10Gbps数据传输的支持，还对机械规格进行了更新。它旨在为相关行业的内部工作文档，即SFF委员会提供一个通用规范，使得所有参与方能够遵循统一的标准来设计和制造高速数据传输设备。此外，SFF-8436是公开供公众评审的，以便收集用户反馈，以便在未来对标准进行迭代改进。该标准的支持主要来自参与的公司成员，这些公司通过遵循SFF-8436的规定，确保他们的产品能够在兼容的环境中无缝运作。购买SFF委员会的文档既可以获取硬拷贝，也可以在线获取，文档的获取地址为ftp://ftp.seagate.com/sff。对于硬件电路开发者而言，这份文档提供了至关重要的设计指南，包括接口尺寸、引脚配置、信号传输标准、功率消耗限制等细节。在进行QSFP+模块或直连电缆的研发时，必须严格遵循SFF-8436的要求，以保证产品的互操作性和可靠性。因此，对于任何涉及高速数据传输和小型化设计的项目，理解和遵循SFF-8436 QSFP+标准都是必不可少的。

Published SFF-8436 Rev 4.1

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 15

Table 3: Pin Function Definition (See Figure 10 for pad dimensions)

Logic Symbol Description Plug

Sequence

Notes

1 GND Ground 1 1

2 CML-I Tx2n Transmitter Inverted Data Input 3

3 CML-I Tx2p Transmitter Non-Inverted Data Input 3

4 GND Ground 1 1

5 CML-I Tx4n Transmitter Inverted Data Input 3

6 CML-I Tx4p Transmitter Non-Inverted Data Input 3

7 GND Ground 1 1

8 LVTTL-I

ModSelL

Module Select 3

9 LVTTL-I

ResetL Module Reset 3

10 Vcc Rx +3.3V Power Supply Receiver 2 2

11 LVCMOS-

I/O

SCL 2-wire serial interface clock 3

12 LVCMOS-

I/O

SDA 2-wire serial interface data 3

13 GND Ground 1 1

14 CML-O Rx3p Receiver Non-Inverted Data Output 3

15 CML-O Rx3n Receiver Inverted Data Output 3

16 GND Ground 1 1

17 CML-O Rx1p Receiver Non-Inverted Data Output 3

18 CML-O Rx1n Receiver Inverted Data Output 3

19 GND Ground 1 1

20 GND Ground 1 1

21 CML-O Rx2n Receiver Inverted Data Output 3

22 CML-O Rx2p Receiver Non-Inverted Data Output 3

23 GND Ground 1 1

24 CML-O Rx4n Receiver Inverted Data Output 3

25 CML-O Rx4p Receiver Non-Inverted Data Output 3

26 GND Ground 1 1

27 LVTTL-O

ModPrsL

Module Present 3

28 LVTTL-O

IntL Interrupt 3

29 Vcc Tx +3.3V Power supply transmitter 2 2

30 Vcc1 +3.3V Power supply 2 2

31 LVTTL-I

LPMode Low Power Mode 3

32 GND Ground 1 1

33 CML-I Tx3p Transmitter Non-Inverted Data Input 3

34 CML-I Tx3n Transmitter Inverted Data Input 3

35 GND Ground 1 1

36 CML-I Tx1p Transmitter Non-Inverted Data Input 3

37 CML-I Tx1n Transmitter Inverted Data Input 3

38 GND Ground 1 1

Note 1: GND is the symbol for signal and supply (power) common for the QSFP+

module. All are common within the QSFP+ module and all module voltages are

referenced to this potential unless otherwise noted. Connect these directly to the

host board signal-common ground plane.

Note 2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and

shall be applied concurrently. Requirements defined for the host side of the Host

Edge Card Connector are listed in Table 6. Recommended host board power supply

filtering is shown in Figures 3 and 4. Vcc Rx Vcc1 and Vcc Tx may be internally

connected within the QSFP+ Module in any combination. The connector pins are each

rated for a maximum current of 500 mA.

Figure 3 shows an example of a complete QSFP+ host PCB schematic with connections to

SerDes and control ICs.

Published SFF-8436 Rev 4.1

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 18

ModPrsL

IntL

4.1.1.1 ModSelL

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire

serial communication commands. The ModSelL allows the use of multiple QSFP+ modules on a

single 2-wire interface bus. When the ModSelL is “High”, the module shall not respond to

or acknowledge any 2-wire interface communication from the host. ModSelL signal input

node must be biased to the “High” state in the module.

In order to avoid conflicts, the host system shall not attempt 2-wire interface

communications within the ModSelL de-assert time after any QSFP+ modules are deselected.

Similarly, the host must wait at least for the period of the ModSelL assert time before

communicating with the newly selected module. The assertion and de-asserting periods of

different modules may overlap as long as the above timing requirements are met.

4.1.1.2 ResetL

The ResetL pin must be pulled to Vcc in the QSFP+ module. A low level on the ResetL pin

for longer than the minimum pulse length (t_Reset_init) initiates a complete module

reset, returning all user module settings to their default state. Module Reset Assert

Time (t_init) starts on the rising edge after the low level on the ResetL pin is

released. During the execution of a reset (t_init) the host shall disregard all status

bits until the module indicates a completion of the reset interrupt. The module indicates

this by asserting “low” an IntL signal with the Data_Not_Ready bit negated. Note that on

power up (including hot insertion) the module should post this completion of reset

interrupt without requiring a reset.

4.1.1.3 LPMode

The LPMode pin shall be pulled up to Vcc in the QSFP+ module. This function is affected

by the LPMode pin and the combination of the Power_over-ride and Power_set software

control bits (Address A0h, byte 93 bits 0,1).

The module has two modes a low power mode and a high power mode. The high power mode

operates in one of the four power classes.

When the module is in a low power mode it has a maximum power consumption of 1.5W. This

protects hosts that are not capable of cooling higher power modules, should such modules

be accidentally inserted.

The modules 2-wire serial interface and all laser safety functions must be fully

operational in this low power mode. The module shall still support the completion of

reset interrupt in this low power mode.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate a power

consumption greater than 1.5W and the module is in low power mode it must reduce its

power consumption to less than 1.5W while still maintaining the functionality above. The

exact method of accomplishing low power is not specified, however it is likely that

either the Tx or Rx or both will not be operational in this state.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate that its power

consumption is less than 1.5W then the module shall be fully functional independent of

whether it is in low power or high power mode.

The Module should be in low power mode if the LPMode pin is in the high state, or if the

Power_ override bit is in the high state and the Power_set bit is also high. The

module should be in high power mode if the LPMode pin is in the low state, or the

Power_override bit is high and the Power_set bit is low. Note that the default state

for the Power_override bit is low.

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