How to Use IIC Module on M68HC08, HCS08, and HCS12 MCUs, Rev. 2
IIC Bus Summary
Freescale Semiconductor4
Figure 3. Control-Byte Structure
2.6 Address Byte
The address byte brings the address information to the slave device. This byte determines the real address
in the EEPROM, to or from the data to be written or read. The address information structure depends on
the connected EEPROM capacity. The EEPROMs up to 16 kbits use one address byte, but EEPROMs with
higher capacity use two byte addresses (address H and address L). Address H is sent first. The structure of
address bytes for a one-byte address are in Figure 4, and in Figure 5 for two byte addresses. The
EEPROMs type 24C16 and 24C512 are used as communication devices.
Figure 4. One Byte Address IIC Write Format
Figure 5. Two Byte Address IIC Write Format
2.7 Acknowledge
The acknowledge bit (ACK) is the low-level impulse on the SDA line during the 9th pulse on the SCL line.
The master always generates the SCL pulses. The receiver generates ACK pulses. This means in the write
operation the slave device generates ACK after each byte transfers. In the read operation, the slave
generates ACK when the control byte and address byte are sent from the master; the master generates ACK
when it receives the data from the slave.
S 1 0 1 0 A10 A9 A8 RW
A
C
K
Control Code Address Bits
Slave Address
START Bit Read/Write Bit
Acknowledge Bit
Control
Byte
Word
Address
Data
Byte
A
C
K
PS
A
C
K
A
C
K
Bus Activity
Master
SDA
Bus Activity
Control
Byte
Word
Address H
A
C
K
PS
A
C
K
A
C
K
Bus Activity
Master
SDA
Bus Activity
Word
Address L
Data
Byte
A
C
K