多核嵌入式系统详解：理论与实践

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《多核嵌入式系统》是一本由CRC Press出版的专业书籍，作为Taylor & Francis Group的系列之一，由Fayez Gebali和Haytham El Miligi两位来自维多利亚大学的编辑共同编撰。该书主要关注于多核嵌入式系统的理论与实践，旨在探索这一领域在现代技术中的关键作用，尤其是在实时性和性能优化方面的挑战。在当前的IT行业中，随着技术的发展，多核嵌入式系统（Multi-Core Embedded Systems）已经成为一个热门话题。这类系统通常指的是将多个处理核心整合到单一芯片或设备中的设计，目的是提高系统的计算能力和响应速度，以满足不断增长的复杂应用需求，如物联网、自动驾驶和工业自动化等。书中涵盖了以下几个核心知识点： 1. **多核架构基础**：介绍了多核处理器的基本原理，包括核心间通信、同步机制和负载均衡策略，这些都是确保系统效率的关键要素。 2. **实时性分析**：讨论了如何在多核环境中保持系统的时间敏感性和实时性能，这对于嵌入式系统的安全性至关重要。 3. **软件开发与编程模型**：本书可能探讨了如何使用像MATLAB®和Simulink®这样的工具进行多核嵌入式系统的软件设计和仿真，强调了模型驱动和并行编程的重要性。 4. **硬件/软件协同设计**：在多核系统中，硬件和软件之间的紧密协作是不可或缺的，本书可能会涉及硬件抽象层（HAL）、中间件和其他优化技术。 5. **案例研究和实践应用**：通过实际案例，读者可以了解到多核嵌入式系统在现实生活中的应用场景，以及如何解决遇到的具体问题。 6. **未来趋势和挑战**：书末可能还会讨论多核嵌入式系统面临的新兴技术和市场趋势，如云计算、边缘计算对多核系统的影响，以及如何适应这些变化以保持竞争力。《多核嵌入式系统》一书不仅提供理论知识，还提供了丰富的实例和实用的指导，对于嵌入式系统工程师、研究人员以及对这一领域感兴趣的读者来说，是一部不可或缺的参考文献。它展示了如何充分利用多核优势，提升嵌入式系统的设计效率和性能，以应对日益复杂的系统需求。

List of Figures xv

3.12 Example of temporal evolution analysis. The graph shows the

number of ﬂits in a router on top side of a 2D mesh net-

work. Each router has globally 120 ﬂit memory of capacity

distributed in ﬁve input and ﬁve out ports. The ﬁgure shows

that, for this traﬃc intensity and scenarios, buﬀer conﬁgura-

tion is oversized and the performance is maintained even if

the router has a smaller memory. . . . . . . . . . . . . . . . 94

3.13 Example of power graph where power state is indicated over

time, router by router. Dark color means high power state.

Router power machine has nine power states and follows ACPI

standard: values from 1 to 4 are ON states, values from 5 to

8 are SLEEP states and value 9 is the OFF state. . . . . . . 95

3.14 Four ON states, f our SLEEP states and OFF state of the

ACPI standard. . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.15 DPM and communication architectures. . . . . . . . . . . . 97

3.16 Clock frequency, supply voltage and power dissipation for the

diﬀerent power states of the ACPI standard. . . . . . . . . . 98

3.17 Percentage of the time the three masters and two slaves and

the bus are in the diﬀerent p ower states during simulation in

a low bus traﬃc test case with local DPM and global DPM. 99

3.18 Energy and bus throughput normalized to the architecture

without DPM. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.19 Qualitative results in terms of bus throughput as a function of

bus traﬃc intensity for diﬀerent DPM architectures and bus

arbitration algorithm. . . . . . . . . . . . . . . . . . . . . . . 100

3.20 Qualitative results in terms of average energy per transfer as

a function of bus traﬃc intensity for diﬀerent D PM architec -

tures and bus arbitration algorithm. . . . . . . . . . . . . . 101

4.1 (a) A conventional 6 × 6 2D mesh and (b) a 6 × 6 irregular

mesh with 1 OIP and 31 normal-sized IPs. . . . . . . . . . . 114

4.2 Possible cycles and turns in 2D mesh. . . . . . . . . . . . . . 117

4.3 Six turns form a cycle and allow deadlock. . . . . . . . . . . 118

4.4 The turns allowed by (a) west-ﬁrst algorithm, (b) north-last

algorithm, and (c) negative-ﬁrst algorithm. . . . . . . . . . . 119

4.5 The six turns allowed in odd-even turn models. . . . . . . . 119

4.6 A minimal routing algorithm ROUT E that is based on the

odd-even turn model. . . . . . . . . . . . . . . . . . . . . . . 120

4.7 The lo c alized algorithm to form extended faulty blocks. . . . 121

4.8 Three examples to form extended faulty blocks. . . . . . . . 122

4.9 E-XY routing algorithm. . . . . . . . . . . . . . . . . . . . . 123

4.10 Eight possible cases of the E-XY in normal mode. . . . . . . 123

4.11 Four cases of the E-XY in abnormal mode: (a) south-to-north,

(b) north-to-south, (c) west-to-east, and (d) east-to-west di-

rection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

xvi List of Figures

4.12 An example to form faulty blocks for Chen and Chiu’s algo-

rithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.13 Two examples of f-rings and f-chains: (a) one f-ring and one

f-chain in a 6 × 6 mesh and (b) one f-ring and eight diﬀerent

types of f-chains in a 10 × 10 mesh. . . . . . . . . . . . . . . 126

4.14 Pseudo codes of the procedure Message-Route Modiﬁed. . . 126

4.15 Pseudo codes of the procedure Normal-Route. . . . . . . . . 127

4.16 Pseudo codes of the procedure Ring-Route. . . . . . . . . . . 128

4.17 Pseudo codes of the procedure Chain-Route Modiﬁed. . . . . 129

4.18 Pseudo codes of the procedure Overlapped -Ring Chain Route. 130

4.19 Examples of Chen and Chiu’s routing algorithm: (a) the rout-

ing paths (RF, CF, and RO) in Normal-Route, and (b) Two

examples of Ring-Route and Chain-Route. . . . . . . . . . . 131

4.20 Traﬃc loads around the OIPs by using (a) Chen and Chiu’s

algorithm [5] (unbalanced), (b) the extended X-Y routing

algorithm [34] (unbalanced), and (c) the OAPR [21] (bal-

anced). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.21 The OAPR: (a) eight default routing cases and (b) some cases

to detour OIPs. . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.22 Restrictions on OIP placements for the OAPR. . . . . . . . 133

4.23 The OAPR design ﬂow: (a) the routing logic in the ﬁve-port

router model, (b) the ﬂowchart of the OAPR design ﬂow, and

4.24 Overview of APSRA design methodology. . . . . . . . . . . 135

4.25 An example of APSRA metho dology: (a) CG, (b) T G, (c)

CDG, (d) ASCDG, and (e) the concurrency of the two loops. 137

4.26 An example of the routing table in t he west input port of node

X: (a) original routing table and (b) compressed routing table. 138

4.27 An example of the compressed routing table in node X with

loss of adapt iv ity: (a) the routing table by merging destina-

tions A and B and (b) the routing table by merging re gions

R1 and R3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.28 OIP placement with diﬀerent sizes and locations. . . . . . . 140

4.29 Eﬀect on latency with central region in NoC. . . . . . . . . 141

4.30 Latency for horizontal shift of positions. . . . . . . . . . . . 141

4.31 Latency for vertical shift of positions. . . . . . . . . . . . . . 142

4.32 OIP placements with diﬀerent orientations. . . . . . . . . . 142

4.33 An example of a 12 × 12 distribution graph. . . . . . . . . . 144

4.34 Latencies of one 3 × 3 OIP placed on a 12 × 12 mesh. . . . 144

4.35 Latencies of one four-unit OIP placed on a 12 × 12 mesh: (a)

horizontal placements and (b) vertical placements. . . . . . 145

4.36 (a) Routing paths without turning to destination D and (b)

Routing paths with two turns to D. . . . . . . . . . . . . . . 146

4.37 TT routing algorithm for one destination D. . . . . . . . . . 147

4.38 XYDT routing algorithm for one destination D. . . . . . . . 148

List of Figures xvii

4.39 Degree priority routing algorithm. . . . . . . . . . . . . . . . 149

4.40 Examples showing the degrees of the nodes A, B, C, and D. 150

4.41 An example of the degree priority routing algorithm. . . . . 150

4.42 Routing tables of nodes 1, 6, 10, C, and X. . . . . . . . . . 150

5.1 Design reﬁnement process. . . . . . . . . . . . . . . . . . . . 157

5.2 Safe asynchronous communication using a handshake. . . . . 160

5.3 Lack of consistent global state with multiple, asynchronous

clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.4 Non-determinism in communication between clock domains. 162

5.5 Example of system communication via shared memory. . . . 162

5.6 System traces and permanent intermittent errors. . . . . . . 165

5.7 Scope reduced to include Master 2 only. . . . . . . . . . . . 166

5.8 Scope reduced to include Master 1 and Master 2 only. . . . 167

5.9 Debug ﬂow charts. . . . . . . . . . . . . . . . . . . . . . . . 168

5.10 Run/stop debug methods. . . . . . . . . . . . . . . . . . . . 175

5.11 Debug abstractions. . . . . . . . . . . . . . . . . . . . . . . . 177

5.12 Debug hardware architecture. . . . . . . . . . . . . . . . . . 179

5.13 Example system under debug. . . . . . . . . . . . . . . . . . 181

5.14 Oﬀ-chip debug infrastructure with software architecture. . . 185

5.15 Physical and logical interconnectivity. . . . . . . . . . . . . . 189

6.1 Our design space exploration approach for system-level NoC

selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.2 Metis-based Neato visualization of the Spidergon NoC lay-

out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.3 Source ﬁle for Scotch partitioning tool. . . . . . . . . . . . 214

6.4 Target ﬁle for Scotch partitioning tool. . . . . . . . . . . . 215

6.5 Application models for (a) 2-rooted forest (SRF), (b) 2-rooted

tree (SRT), (c) 2-node 2-rooted forest(MRF) application task

graphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6.6 The Mpe g4 decoder task graph. . . . . . . . . . . . . . . . . 218

6.7 The Spidergon top ology translates to simple, low-cost VLSI

implementation. . . . . . . . . . . . . . . . . . . . . . . . . . 220

6.8 Edge dilation for (a) 2-rooted and (b) 4-rooted forest, (c) 2

node-disjoint and (d) 4 node-disjoint trees, (e) 2 node-disjoint

2-routed and (f) 4 node-disjoint 4-route d forests in function

of the network size. . . . . . . . . . . . . . . . . . . . . . . . 222

6.9 Relative e dge expansion for 12-node Mpeg4 for diﬀerent target

graphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.10 Model of the router used in the considered NoC architectures. 225

6.11 Maximum throughput as a function of the network size for (a)

2-rooted forest, (b) 4-rooted forest (SRF), (c) 2-rooted tree,

(d) 4-rooted tree (SRT), (e) 2-node 2-rooted forest and (f)

4-node 2-rooted forest (MRF) and diﬀerent NoC topologies. 226

xviii List of Figures

6.12 Amount of memory required by each interconnect. . . . . . 228

6.13 (a) Task execution time and (b) average pat h length for

Mpeg4 traﬃc on the considered NoC architec tures. . . . . . 228

6.14 Average throughput on router’s output port for (a) Spidergon,

(b) ring, (c) mesh and (d) unbuﬀere d crossbar architecture. 230

6.15 Network RTT as a function of the initiators’ oﬀered load. . 231

6.16 Future work: dynamic scheduling of tasks. . . . . . . . . . . 233

7.1 Input code: the depth of each loop nest L

is n ( n loops), A

is n dimensional. . . . . . . . . . . . . . . . . . . . . . . . . 247

7.2 Code example and its iteration domain. . . . . . . . . . . . 248

7.3 An example of loop fusion. . . . . . . . . . . . . . . . . . . . 249

7.4 An example of tiling. . . . . . . . . . . . . . . . . . . . . . . 250

7.5 An example of buﬀer allocation. . . . . . . . . . . . . . . . . 250

7.6 An example of three loop nests. . . . . . . . . . . . . . . . . 251

7.7 Partitioning after loop fusion. . . . . . . . . . . . . . . . . . 252

7.8 Diﬀerence between positive and lex icographically positive de-

pendence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

7.9 Tiling technique. . . . . . . . . . . . . . . . . . . . . . . . . 254

7.10 Buﬀer allocation for array B. . . . . . . . . . . . . . . . . . 255

7.11 Classic partitioning. . . . . . . . . . . . . . . . . . . . . . . . 257

7.12 Diﬀerent partitioning. . . . . . . . . . . . . . . . . . . . . . 257

7.13 Buﬀer allocation for array B with new partitioning. . . . . . 258

7.14 Sub-division of processor P

’s blo ck. . . . . . . . . . . . . . 259

7.15 Elimination of modulo operators. . . . . . . . . . . . . . . . 260

7.16 Execution order (a) without fusion (b) after fusion and (c)

after unimodular transformation. . . . . . . . . . . . . . . . 261

7.17 StepNP platform. . . . . . . . . . . . . . . . . . . . . . . . . 262

7.18 DCache hit ratio results for four CPUs. . . . . . . . . . . . . 263

7.19 Processing time results for four CPUs. . . . . . . . . . . . . 264

8.1 Abstraction levels of multi-core software directives, utilities

and tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

8.2 Threading structure of fork-join model. . . . . . . . . . . . . 273

8.3 Work distribution model. . . . . . . . . . . . . . . . . . . . . 274

8.4 Pipeline threading model. . . . . . . . . . . . . . . . . . . . 274

8.5 Scheduling threading structure. . . . . . . . . . . . . . . . . 277

8.6 Parallel functions in thread building blocks. . . . . . . . . . 281

8.7 Program ﬂow in host and device for NVIDIA CUDA. . . . . 283

8.8 Stream structures using ﬁlters. . . . . . . . . . . . . . . . . . 285

8.9 OC program in Listing 8.2 distributed into two locat ions. . . 290

8.10 LUSTRE to TTA implementation ﬂow. . . . . . . . . . . . . 292

8.11 Weakly endochronous program with diamond property. . . . 295

8.12 Process-based threading model. . . . . . . . . . . . . . . . . 296

8.13 Fine grained thread structure of polychrony. . . . . . . . . . 297

List of Figures xix

8.14 SDFG-based multi-threading for SIGNAL. . . . . . . . . . . 298

8.15 TAX YS tool structure with event handling and code genera-

tion [23]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

8.16 Task precedence in a multi-rate real time application [37]. . 301

9.1 Example of HMC-SoC. . . . . . . . . . . . . . . . . . . . . . 310

9.2 Ideal software organization. . . . . . . . . . . . . . . . . . . 312

9.3 Parallelization of an application. . . . . . . . . . . . . . . . . 313

9.4 BSP-based software organization. . . . . . . . . . . . . . . . 315

9.5 BSP-based application development. . . . . . . . . . . . . . 316

9.6 BSP-based bo ot-up sequence strategies. . . . . . . . . . . . 316

9.7 Software organization of a GPOS-based application. . . . . . 318

9.8 GPOS-based application development. . . . . . . . . . . . . 319

9.9 GPOS-based boot-up sequence. . . . . . . . . . . . . . . . . 320

9.10 Software organization of a generated application. . . . . . . 323

9.11 Examples of computations models. . . . . . . . . . . . . . . 324

9.12 Tasks graph with RTOS elements. . . . . . . . . . . . . . . . 325

9.13 Component architecture. . . . . . . . . . . . . . . . . . . . . 326

9.14 Component-based OS software organization. . . . . . . . . . 327

9.15 Example of a dependency graph. . . . . . . . . . . . . . . . 328

10.1 Pipelined micro-archite c ture of an embedded variant of Ultra-

SPARC T1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

10.2 Trap logic unit. . . . . . . . . . . . . . . . . . . . . . . . . . 352

10.3 Chip block diagram. . . . . . . . . . . . . . . . . . . . . . . 353

10.4 Archit e c ture of autonomous hardware power saving logic. . 355

10.5 Global power management unit. . . . . . . . . . . . . . . . . 356

11.1 picoBus interconnect structure. . . . . . . . . . . . . . . . . 371

11.2 Processor structure. . . . . . . . . . . . . . . . . . . . . . . . 372

11.3 VLIW and execution unit structure in each processor. . . . 372

11.4 Tool ﬂow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

11.5 Behavioral simulation instance . . . . . . . . . . . . . . . . . 380

11.6 Example of where-deﬁned program analysis. . . . . . . . . . 384

11.7 Design browser display. . . . . . . . . . . . . . . . . . . . . . 385

11.8 Diagnostics output from 802.16 PHY. . . . . . . . . . . . . . 386

11.9 Hardening approach. . . . . . . . . . . . . . . . . . . . . . . 389

11.10 Software implementation of Viterbi decoder and testbench. . 390

11.11 Partially hardened implementation of Viterbi decoder and

testbench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

11.12 Fully hardened implementation of Vite rbi decoder and test-

bench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

11.13 Femtocell system. . . . . . . . . . . . . . . . . . . . . . . . . 393

11.14 Femtocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

11.15 Femtocell reference board. . . . . . . . . . . . . . . . . . . . 395

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