TI DS90CR288A：28位LVDS数据传输芯片，85MHz高速解决方案

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TI的DS90CR287/DS90CR288A是一款专为解决高速串行通信问题而设计的高性能芯片套件。它们主要针对28位数据传输，支持LVCMOS/LVTTL接口，适用于要求高带宽和低电磁干扰（EMI）的应用场景。 DS90CR287是发射器，其核心功能是将20到85 MHz范围内的28位LVCMOS/LVTTL数据转换成四个LVDS（低电压差分信号）数据流。发射器使用一个与数据并行传输的锁相环（PLL）产生的28位时钟，确保每周期稳定采样输入数据。它具有50%的接收器输出时钟占空比，降低了功耗，并且能在±1V的共模范围内工作，典型情况下，发射器的LVDS输出摆幅为345 mV，有助于减小电磁干扰。 DS90CR288A是接收器，负责接收这四个LVDS数据流并将它们还原成28位的LVCMOS/LVTTL数据。在85 MHz的传输时钟下，可以实现高达2.38 Gbps的数据传输速率（即每秒297.5 Mbytes），这极大地提高了数据吞吐量。接收器的特点还包括一个上升沿数据 strobe 功能，用于精确控制数据传输，有助于减少数据错误和提高系统效率。此外，由于采用了窄数据总线设计，这有助于缩小电缆尺寸，降低安装成本。该芯片组符合TIA/EIA-644 LVDS标准，这意味着它在设计上遵循了业界通用的接口规范，便于与其他兼容设备集成。它采用低功耗的解决方案，无需额外的外部元件就能实现锁相环功能，使得整个系统设计更加简洁高效。 DS90CR287/DS90CR288A套件以紧凑的56引脚TSSOP封装形式提供，具有低轮廓设计，适合空间有限的应用场合。用户可以通过TI官方网站获取样品和相关文档，以便于评估和实施这些高性能的串行通信解决方案。总结来说，TI的DS90CR287/DS90CR288A是一对强大的数据传输组件，通过其独特的设计和性能特性，满足了高速、低功耗、小型化和EMI控制的需求，是工业界广泛应用于如CameraLink等高速接口的理想选择。

DS90CR287, DS90CR288A

www.ti.com

SNLS056G –OCTOBER 1999–REVISED MARCH 2013

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ

(1)

Max Units

LLHT LVDS Low-to-High Transition Time Figure 7 0.75 1.5 ns

LHLT LVDS High-to-Low Transition Time Figure 7 0.75 1.5 ns

TCIT TxCLK IN Transition Time Figure 9 1.0 6.0 ns

TPPos0 Transmitter Output Pulse Position for Bit0 Figure 19 f = 85 MHz −0.20 0 0.20 ns

TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns

TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns

TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns

TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns

TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns

TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns

TCIP TxCLK IN Period Figure 10 11.76 T 50 ns

TCIH TxCLK IN High Time Figure 10 0.35T 0.5T 0.65T ns

TCIL TxCLK IN Low Time Figure 10 0.35T 0.5T 0.65T ns

TSTC TxIN Setup to TxCLK IN Figure 10 f = 85 MHz 2.5 ns

THTC TxIN Hold to TxCLK IN Figure 10 0 ns

TCCD TxCLK IN to TxCLK OUT Delay Figure 12 T

= 25°C, V

= 3.3V 3.8 6.3 ns

TPLLS Transmitter Phase Lock Loop Set Figure 14 10 ms

TPDD Transmitter Powerdown Delay Figure 17 100 ns

TJIT TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement) 2 ns

(1) Typical values are given for V

= 3.3V and T

= +25°C.

Product Folder Links: DS90CR287 DS90CR288A

DS90CR287, DS90CR288A

SNLS056G –OCTOBER 1999–REVISED MARCH 2013

www.ti.com

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ

(1)

Max Units

CLHT CMOS/TTL Low-to-High Transition Time Figure 8 2 3.5 ns

CHLT CMOS/TTL High-to-Low Transition Time Figure 8 1.8 3.5 ns

RSPos0 Receiver Input Strobe Position for Bit 0 Figure 20 f = 85 MHz 0.49 0.84 1.19 ns

RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns

RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns

RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns

RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns

RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns

RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns

RSKM RxIN Skew Margin

(2)

Figure 21 f = 85 MHz 290 ps

RCOP RxCLK OUT Period Figure 11 11.76 T 50 ns

RCOH RxCLK OUT High Time Figure 11 f = 85 MHz 4 5 6.5 ns

RCOL RxCLK OUT Low Time Figure 11 3.5 5 6 ns

RSRC RxOUT Setup to RxCLK OUT Figure 11 3.5 ns

RHRC RxOUT Hold to RxCLK OUT Figure 11 3.5 ns

RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, V

= 3.3V

(3)

Figure 13 5.5 7 9.5 ns

RPLLS Receiver Phase Lock Loop Set Figure 15 10 ms

RPDD Receiver Powerdown Delay Figure 18 1 μs

(1) Typical values are given for V

= 3.3V and T

= +25°C.

(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows

LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than 150 ps).

(3) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver

(RCCD). The total latency for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.

Product Folder Links: DS90CR287 DS90CR288A

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