OIF-ITLA-MSA-01.3: 2015年光学互连论坛通用协议

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"OIF-ITLA-MSA-01.3-MSA通用协议.pdf是2015年由光学互连论坛(OIF)创建并批准的集成可调激光器组件(MSA)的实施协议。该协议旨在促进全球光学互联系统产品的兼容性，并与多个国际标准组织建立了工作关系或正式联络。" 本文档详细阐述了Integrable Tunable Laser Assembly (ITLA)的多源协议(MSA)，这是一个关键的光学通信技术，用于构建高效、成本效益高且可靠的光网络。OIF，即光学互连论坛，是一个由超过100家全球领先的运营商和供应商组成的非营利组织，其主要任务是推动可互操作、经济且坚固的光学互联系统及其相关技术的部署。光学互联系统是基于路由器和数据交换机的数据网络，这些设备通过光学网络元素相互连接。为了在全球范围内实现光学互联系统产品的兼容性，OIF积极支持并扩展国家和国际标准机构的工作。它与众多业界组织建立了合作关系，包括CFP-MSA、COAST、Ethernet Alliance、Fibre Channel T11、IEEE 802.1、IEEE 802.3、IETF、InfiniBand、ITU-T SG13、ITU-T SG15、MEF、ONF、RapidIO、SAST 10、SFF委员会、TMF和TMOC等。 OIF的MSA通用协议如OIF-ITLA-MSA-01.3，对ITLA的技术规范、接口标准、性能指标和测试方法等方面进行了规定，确保不同厂商的产品能够无缝协同工作。ITLA是一种可集成、可调谐的激光器组件，对于现代光纤通信系统，尤其是数据中心和长途光网络的灵活带宽管理和高效频谱利用至关重要。这份2015年的协议文档涵盖了ITLA的设计原则、功能特性、电气和光学性能参数、机械接口、热管理以及可靠性要求。它还可能包含了关于测试程序和一致性验证的详细信息，以确保所有参与MSA的制造商都能遵循一致的标准，从而实现设备间的互操作性。 OIF-ITLA-MSA-01.3是光学通信领域的重要参考资料，对于设计、开发和部署基于ITLA技术的光网络产品的企业和工程师具有极高的价值。这份协议的实施有助于推动行业的标准化进程，降低互操作性的难题，加速技术创新，并最终促进全球光通信市场的繁荣。

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6.3 Communication Overview

The following diagram (Figure 6.3-1) depicts the communication process.

Figure 6.3-1 Three Layer Communication Diagram

Assume the host has a request to transmit to the module (Host’s Request). The request is

first encoded as a 28-bit command packet in the Host Driver’s application layer. The

command is then framed as a 32-bit packet in the host driver’s transport layer. The

framing operation includes the addition of a BIP-4

checksum. Finally, the host driver’s

physical interface (RS232 shown) encodes the 32 bit packet as 4 ten bit

RS232

“characters” and transmits in across the TxD line to the module.

The module’s physical layer receives 40 bits and de-codes them by removing the RS232

start and stop bits. The resulting 32-bit frame is delivered to the transport layer where

checksum is checked for consistency. Assuming no error is generated, the 28-bit

command packet is delivered to the module’s application layer where the command is

decoded and executed.

The command execution will generate a response when complete

. The response packet

consists of 26 bits.

The response packet is delivered to the module’s transport layer which frames the packet

by pre-pending a checksum, communication error (CE). The resulting 32-bit packet is then

delivered to the module’s physical layer where it is then encoded as 40 bits.

Bit Interleaved Parity (4 bits)

Note each byte to be transmitted by RS232 is encapsulated by a start and stop bit thus pre-

pending 1 bit and post-pending 1 bit for a total of 10 bits for each byte to be transmitted.

Note that an initial response may also be generated for commands whose execution time

exceeds the command response timeout period. The host can either poll for completion of the

command or have pre-configured the module to issue a service request (SRQ) upon completion

of the command.

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The host then receives the 4 RS232 characters and performs the inverse operations as the

packet moves up the host’s layer hierarchy.

6.3.1 Physical Interfaces

The communications interface supports only one physical layer protocol, RS232.

6.4 Command Overview

The commands to the module consist of a 9-bit operation followed by 2 bytes of optional

data. Alternatively, the command can be thought of as one read/write bit followed by an 8-

bit register number followed by 2 bytes of optional data. See Figure 6.4-1. The register

paradigm will be used in this document.

Figure 6.4-1: Paradigms for Module Control

Command Paradigm

9 bit command

Data byte 1

Data byte 2

Read/Write Bit

8 bit register

number

Data byte 1

Data byte 2

There are 256 directly accessible registers (0x00 to 0xFF) in the primary register address

space. The OIF-IA allocates the first 32 registers (0x00 to 0x1F) for generic module

operations for all module types. Another 96 registers (0x20-0x7f) are reserved for device

type “CW Laser Int Assy”. Finally, the remaining 128 registers (0x80-0xFF) are provided

as manufacturing specific registers.

The following example shows how the module’s status would be read.

Table 6.3.1-1: Example Reading Module Status

Command (Host to Module)

Response (Module to Host)

Operation

Data

Bytes

(15:0)

Status

Data Bytes (15:0)

Read

0x20 (StatusF)

0x0000

0x00 (Ok)

0x20 (StatusF)

0x0000

Note: Example shows that the module status is 0x0000 as returned in the response data.

6.4.1 Command Execution Overlap

The application layer provides support for pending operations especially useful for

operations that can take a significant period of time to complete

If a command is issued to the module that results in a long time to complete, the module

will return a response packet within the specified time out period for the module and flag

the operation as pending

. The interface is now free to respond to additional commands.

The host can determine when the pending operation completes by polling the NOP register

(0x00). The NOP register returns the pending operation status as well as any error

conditions. Note that the module can be configured to generate an SRQ (Service

Request) when a pending operation terminates operation in an error state. See §9.4.1 and

§9.1.2.

Channel tuning is an example of a command which can take from 5ms to 15s to achieve

depending on laser technology utilized.

Some other interfaces such as the 300-pin transponder MSA do not allow command execution

overlap.

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6.4.2 Extended Addressing

Extended addressing provides an additional memory space (22 address bits) in addition to

the primary 256 registers (8-bit address space).

The extended addressing feature consists of three registers described in Table 6.4.2-1.

Table 6.4.2-1: Extended Address Register Description

Description

Fields

Configuration

Defines basic configuration for the extended

address

Defines the

 address space

 high order address bits

Address

Address of field in either physical or virtual

memory space

Defines the 16 low order address

bits

Contents

Reading from this register returns data

stored in this field 16 bits at a time

Write to this register stores data into this

field 16 bits at a time

16 bit data value

Once the configuration and address registers are configured, the host may issue a series

of read or write commands to the (indirect contents register) thereby accessing the

memory location pointed to by the indirect register. The locations may map to physical or

virtual memory spaces.

The configuration register and address registers are usually pre-configured when one of

the primary registers is accessed which holds an object longer than a 16-bit integer.

For example, the device type of the laser is stored in register. The DevTyp register (0x01)

requires the use of the extended address register. Table 6.4.2-2 shows an example where

the DevTyp register is read and the module returns the 8-character string “CW ITLA\0”.

The table shows a seventh entry showing what happens if the read extends beyond the

available string length.

Table 6.4.2-2: Extended Address Register READ Example

Command (Host to Module)

Response (Module to Host)

Operation

Data

Bytes

(15:0)

Status

Data Bytes (15:0)

Read

0x01 (DevTyp)

0x0000

0x02 (AEA-flag)

0x01 DevTyp

0x0008

(# bytes in string)

Note: When the Read is completed, registers (0x09, and 0x0A) are configured to point to proper field.

Read

0x0B (AEA-EAR)

0x0000

0x00

0x0B (AEA-EAR)

0x4357 (“CW”)

Read

0x0B (AEA-EAR)

0x0000

0x00

0x0B (AEA-EAR)

0x2049 (“ I”)

Read

0x0B (AEA-EAR)

0x0000

0x00

0x0B (AEA-EAR)

0x544C (“TL”)

Read

0x0B (AEA-EAR)

0x0000

0x00

0x0B (AEA-EAR)

0x4100 (“A\0”)

Read

0x0B (AEA-EAR)

0x0000

0x01 (XE-flag)

0x0B (AEA-EAR)

0x0000

Writing to an extended address field is handled in much the same way. The initial write

causes the configuration and address registers to be preset to the appropriate values.

Writing to the extended address register then stores the 16 bit values sequentially into the

field.

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6.4.3 Data Types

All of the general registers hold 16-bit data values or serve as pointers to a sequence of

bytes (extended addressing mode). All values are stored as big endian, two’s

complement

6.4.3.1 Two Byte Data Values

Data is represented in the registers as either signed or unsigned 16 bit integers.

Note that single byte values would be stored with the appropriate leading zeros.

Real values are stored with an implied decimal point location. For instance, the value

“12.3 dBm” would be stored as 123

in a field and has an implied formatting of one

decimal place.

6.4.3.2 Multi-byte Fields

Fields holding data longer than 16 bits are stored as a sequence of bytes and

accessed through the extended addressing register.

ASCII strings are terminated with a null. Note that the extended address register

allows the host to read beyond a null termination but not beyond the maximum field

size.

Integers, floats, or structures are stored as a sequence of bytes

6.4.4 Execution Error Field Conditions

The reason for an execution error (XE) can be determined by reading the NOP/Status

the error conditions.

Error Field

Symbol

Meaning

0x00

Ok, no errors

0x01

RNI

The addressed register is not implemented

0x02

RNW

0x03

RVE

error; contents unchanged

0x04

CIP

Command ignored due to pending operation

0x05

CII

Command ignored while module is initializing, warming up, or contains an

invalid configuration

0x06

ERE

Extended address range error (address invalid)

0x07

ERO

Extended address is read only

0x08

EXF

Execution general failure

0x09

CIE

Command ignored while module’s optical output is enabled (carrying

traffic)

0x0A

IVC

Invalid configuration, command ignored

0x0A-0x0E

Reserved for future expansion

0x0F

VSE

Vendor specific error

6.5 Command & Module Features

6.5.1 Module Reset

The module provides four ways to accomplish reset.

Reset Technique

Resulting Action

For instance, the number 256

(0x0100) is stored as the byte sequence 0x01, 0x00. The string

“HI” is stored as the series of bytes: 0x48 (‘H’), 0x49 (‘I’), 0x00(‘\0’).

Note that an RVE error can occur if a field can only take on certain discrete values and an

invalid value is written. For instance, a particular module may only support 25GHz or 50GHz grid

intervals. If an interval of 30GHz is written and is not supported, the module will return an RVE

error code.

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Hardware

Module Select

(when MS* de-asserted and then

re-asserted (specifically the low

to high transition))

Clears communication input buffers, may reset baud rate to

default (See §7.2.1). Does not affect AEA registers.

Reset (RST* low)

Traffic interrupting – reboots module.

Software

ResEna (0x32) (SR Bit = 1)

Aborts transfers in progress (FW download, AEA transfers)

ResEna (0x32) (MR Bit = 1)

Traffic interrupting – reboots module.

6.5.2 Communication Error Detection

Communication error detection occurs on the module and host sides of the communication

interface.

6.5.2.1 Detection by Module

The module examines the in-bound packets (host to module) to see if the checksum

(see §8.2) is consistent. An inconsistency results in a unprocessed response packet

with the CE flag asserted in the out-bound packet.

When the host observes the CE flag, the last out-bound packet should be resent.

6.5.2.2 Detection by Host

The host examines the response packets for consistency by checking the checksum

(see §8.2) for the out-bound packet (module to host). If the checksum is inconsistent,

the host may request the module’s last response to be retransmitted by setting the

LstRsp bit in the Host to Module Packet. This can also be accomplished by reading

the deprecated LstResp (0x13) register.

6.5.3 Execution Error Detection

Execution errors occur when the module is unable to execute the requested command.

The module encodes the XE flag bit (execution error flag) in the response packet. When

the host detects an XE flag in the response packet, it can read the NOP (0x00) register to

determine the error field condition. The reasons for failure to execute a command are

enumerated in §6.4.4-Execution Error Field Conditions.

6.5.4 Module Signaling Line

The module has one hardware line to signal its status, SRQ*.

The SRQ* line is used to signal fatal conditions, warning conditions, or other module

service request needs such as an execution error (XE) for a command processing in the

background (pending operation). The SRQ* line, once asserted, remains asserted until the

status register is cleared.

Alarm or fatal conditions can be determined by reading the status registers (See §9.5.1).

6.5.5 Non-Volatile Default Configuration

The command interface allows the current module configuration to be saved as the default

configuration. The default configuration is restored upon hard reset (See §6.5.1 Module

Reset) or upon power up. In the event of loss of power or hard reset during a save

configuration request, the module’s default configuration will remain unchanged. See

(§9.4.9 General Module Configuration (GenCfg 0x08) [RW]).

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