OIF-ITLA-MSA-01.2：光模块通用协议推动通信设备开发

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OIF-ITLA-MSA-01.2文档是关于光模块通用协议的重要参考资料，由Optical Internetworking Forum（OIF）制定并批准。OIF是一个国际性的非盈利组织，拥有超过80家会员公司，其中包括全球领先的运营商和供应商。它的目标是推动可互操作、成本效益高且健壮的光网络部署，以及与其相关的技术发展。该协议关注的核心是Integrable Tunable Laser Assembly (ITLA)，这是一种集成可调激光器的组件，它在通信设备的软件开发过程中扮演关键角色。光模块作为光网络中的基本单元，它们之间的兼容性对于构建高效网络至关重要。通过与IEEE 802.1、IEEE 802.3ba、IETF、IP/MPLS论坛、IPv6 Forum、ITU-SG13、ITU-T SG15、MEF、ATIS-OPTXS、ATIS-TMOC、TMF以及XFP MSA Group等国际标准组织建立合作关系，OIF确保了这些设备之间的标准化接口，从而简化了网络设计和管理。 OIF-ITLA-MSA-01.2文档涵盖了光模块的接口定义、性能指标、测试方法以及认证流程，帮助开发人员在遵循行业规范的同时，实现产品的互通性和一致性。这份协议不仅规定了物理层规范，还可能包括数据链路层和网络层的交互指南，使得不同厂商生产的光模块能够在各种网络环境中无缝协作。要获取更多关于这个协议的详细信息，可以访问OIF的官方网站www.oiforum.com或联系OIF，地址位于48377 Fremont Blvd.。通过这些资源，开发者能够了解如何在他们的产品中实现与OIF标准的兼容，从而加速光网络的部署，并确保其在全球范围内的广泛接受和成功应用。

OIF-ITLA-MSA-01.2

Integrable Tunable Laser Assembly Multi Source Agreement

www.oiforum.com 16

6.4.2 xtended Addressing

e primary 256 registers (8-bit address space).

The extended add Table 6.4-2.

ter

Extended addressing provides an additional memory space (22 address bits) in addition

ressing feature consists of three registers described in

Table 6.4-2: Extended Address Regis Description

Configuration

nfiguration for the extended

 address space

 high order address bits

Defines basic co

address

Defines the

Address

Address of field in either physical or virtua

memory space

l order address

bits

Defines the 16 low

Contents

ns data

stored in this field 16 bits at a time

16 bit data value

Reading from this register retur

Write to this register stores data into this

field 16 bits at a time

Once the configuration and address registers are configured, the host may issue a series

f read or write commands to the (indirect contents register) thereby accessing the

)

xtended address register. Table 6.4-3 shows an example where

the DevTyp register is read and the module returns the 8-character string “CW ITLA\0”.

The table shows tends beyond the

available string

.4-3: E Addr ister REA le

memory location pointed to by the indirect register. The locations may map to physical or

virtual memory spaces.

The configuration register and address registers are usually pre-configured when one of

the primary registers is accessed which holds an object longer than a 16-bit integer.

For example, the device type of the laser is stored in register. The DevTyp register (0x01

requires the use of the e

a seventh entry showing what happens if the read ex

length.

Table 6 xtended ess Reg D Examp

Command (Host to Module) Response (Module to Host)

Operation Register

Data

Bytes

(15:0)

Status Register Data Bytes (15:0)

Read 0x01 (DevTyp) 0x0000 0x02 (AEA-flag)

ng)

0x01 DevTyp

0x0008

(# bytes in stri

Note: Wh p iste 09, and 0x0A) oi en the Read is com leted, reg rs (0x are configured to p nt to proper field.

2 Read 0x0B (AEA-EAR) 0x0000 0x00 0x0B (AEA-EAR) 0x4357 (“CW”)

3 Read 0x0B (AEA-EAR) 0x0000 0x00 0x0B (AEA-EAR) 0x2049 (“ I”)

4 Read 0x0B (AEA-EAR) 0x0000 0x00 0x0B (AEA-EAR) 0x544C (“TL”)

5 Read 0x0B (AEA-EAR) 0x0000 0x00 0x0B (AEA-EAR) 0x4100 (“A\0”)

6 Read 0x0B (AEA-EAR) 0x0000 0x01 (XE-flag) 0x0B (AEA-EAR) 0x0000

g to an extended address field is handled in much the same way. The initial write

auses the configuration and address registers to be preset to the appropriate values.

extended address register then stores the 16 bit values sequentially into the

Writin

Writing to the

field.

OIF-ITLA-MSA-01.2

Integrable Tunable Laser Assembly Multi Source Agreement

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6.4.3 ata Types

ld 16-bit data values or serve as pointers to a sequence of

bytes

compl

6.4.3.1

All of the general registers ho

(extended addressing mode). All values are stored as big endian, two’s

ement

Two Byte Data Values

Data is represented in the registers as either signed or unsigned 16 bit integers.

Note that single byte values would be stored with the appropriate leading zeros.

ored with an implied decimal point location. For instance, the value

one

6.4.3.2

Real values are st

“12.3 dBm” would be stored as 123

in a field and has an implied formatting of

decimal place.

Multi-byte Fields

Fields holding data longer than 16 bits are stored as a sequence of bytes and

accessed through the extended addressing register.

dress register

llows the host to read beyond a null termination but not beyond the maximum field

6.4.4 E rro Conditions

eason for an execu ading the NOP/Status

ter (NOP . Bit ble describes

conditions.

ASCII strings are terminated with a null. Note that the extended ad

size.

Integers, floats, or structures are stored as a sequence of bytes

xecution E r Field

The r tion error (XE) can be determined by re

regis

the error

0x00) s 3:0 encode the error field value. The following ta

Error Field Symbol Meaning

0x00 OK Ok, no errors

0x01 RNI The addressed register is not implemented

0x02 RNW Register not write-able; register cannot be written (read only)

0x03 RVE

error; contents unchanged

0x04 CIP Command ignored due to pending operation

0x05 CII

Command ignored while module is initializing, warming up, or contains

invalid configuration

0x06 ERE Extended address range error (address invalid)

0x07 ERO Extended address is read only

0x08 EXF Execution general failure

0x09 CIE

ical output is enabled (carrying Command ignored while module’s opt

traffic)

0x0A IVC Invalid configuration, command ignored

0x0A-0x0E -- Reserved for future expansion

0x0F VSE Vendor specific error

6.5 Command & Module Features

6.5.1 Module

o c

Reset

The m

dule provides four ways to a complish reset.

Reset Technique Resulting Action

For instance, the number 256

(0x0100) is stored as the byte sequence 0x01, 0x00. The string

“HI” is stored as the series of bytes: 0x48 (‘H’), 0x49 (‘I’), 0x00(‘\0’).

Note that an RVE error can occur if a field can only take on certain discrete values and an

invalid value is written. For instance, a particular module may only support 25GHz or 50GHz grid

intervals. If an interval of 30GHz is written and is not supported, the module will return an RVE

error code.

OIF-ITLA-MSA-01.2

Integrable Tunable Laser Assembly Multi Source Agreement

www.oiforum.com 18

Module Select

Clears communication input buffers, may reset baud rate to

(when MS* de-asserted and then

re-asserted (specifically the low

to high transition))

default (See §7.2.1). Does not affect AEA registers.

Hardware

Reset (RST* low) Traffic interrupting – reboots module.

ResEna (0x32) (SR Bit = 1) Aborts transfers in progress (FW download, AEA transfers)

Software

ResEna (0x32) (MR Bit = 1) Traffic interrupting – reboots module.

6.5.2 Communication Error Detection

Comm on

interface.

unication error detection occurs on the module and host sides of the communicati

6.5.2.1 Detection by Modu

last out-bound packet should be resent.

The module examines the in-bound packets (host to module) to see if the checksum

(see §8.2) is consistent. An inconsistency results in a unprocessed response packet

with the CE flag asserted in the out-bound packet.

When the host observes the CE flag, the

6.5.2.2 Detection by Host

The host examines the response packets for consistency by checking the checksum

(see §

he requested command.

he module encodes the XE flag bit (execution error flag) in the response packet. When

r to

6.5.4 odule Signaling Line

nditions, warning conditions, or other module

cution error (XE) for a command processing in the

6.5.5 on-Volatile Default Configuration

The command interface allows the current module configuration to be saved as the default

configuration. The default configuration is restored upon hard reset (See §6.5.1 Module

Reset) or upon power up. In the event of loss of power or hard reset during a save

configuration request, the module’s default configuration will remain unchanged. See

(§9.4.9 General Module Configuration (GenCfg 0x08) [RW]).

8.2) for the out-bound packet (module to host). If the checksum is inconsisten

the host may request the module’s last response to be retransmitted by setting the

LstRsp bit in the Host to Module Packet. This can also be accomplished by readin

the deprecated LstResp (0x13) register.

6.5.3 Execution Error Detectio

Execution errors occur when the module is unable to execute t

the host detects an XE flag in the response packet, it can read the NOP (0x00) registe

determine the error field condition. The reasons for failure to execute a command are

enumerated in §6.4.4-Execution Error Field Conditions.

The module has one hardware line to signal its status, SRQ*.

The SRQ* line is used to signal fatal co

ervice request needs such as an exes

background (pending operation). The SRQ* line, once asserted, remains asserted until the

status register is cleared.

Alarm or fatal conditions can be determined by reading the status registers (See §9.5.1

OIF-ITLA-MSA-01.2

Integrable Tunable Laser Assembly Multi Source Agreement

www.oiforum.com 20

Table 7.1-2 Pin Functions

Pin Numbers Symbol Type Name Description

5,7 GND Power Ground

Ground

Note: Ground pins are tied together

internally to the module.

1,3 PS+3.3V Power +3.3V Supply

3.3V Power Supply

Note: Pins are tied together internally

to the module.

9,11 PS-5.2V Power -5.2V Supply

-5.2V Power Supply

Note: Pins are tied together internally

to the module.

12 RST*

LVTTL input,

active low

Reset

Purpose: Disables laser output and

holds the module in RESET

Initial State: Any – user application

specific

Action: Laser OFF, TEC OFF,

Module CPU held in RESET,

Communication protocol is OFF

Resultant State: High, Must remain

high for laser to operate

Attributes: When active, lowest

current draw from the module.

2 DIS*

LVTTL input,

active low

Disable module’s

optical output

Purpose: Provide hardware control to

kill laser output.

Initial State: Any – user application

specific

Action: High = laser output controlled

by protocol; Low = laser output OFF

Resultant State: When DIS*

asserted, communication protocol is

ON, software enable (SENA) reset.

Attributes: Bypasses communication

protocol to turn laser OFF. Re-

enabling of the laser requires setting

SENA. Otherwise does not interfere

with module settings.

4 SRQ*

LVTTL output,

active low

Programmable

module service

request

Purpose: General purpose service

request.

Initial State: High (No service

requested)

Action: Generates request for service

as required to report a variety of

conditions by setting line low. SRQ*

is asserted when the result of the

status (0x20,0x21) OR’d with SRQT

trigger (0x28) is non-zero.

Resultant State:

· Communication protocol is ON

· SRQ* conditions can be read and

cleared through interface

Attributes: SRQ conditions (and

limits) are software configurable and

can be re-configured by the user

through the interface. Status bits

must be cleared to de-assert SRQ*.

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