Xilinx Vivado UG1197：2018.2版的高效层次设计方法指南

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Xilinx的Vivado白皮书（UG1197）是一份针对Vivado Design Suite HLx版本的详细指南，特别是UltraFast高层次生产力设计方法。这份2018.2版文档旨在帮助用户提升FPGA设计的效率和质量，通过以下关键要素实现10-15倍的生产力提升： 1. **并行开发流程**：强调利用并行开发来保护和利用宝贵的知识产权（IP），这种IP开发方法有助于产品的市场差异化。 2. **基于C语言的设计流程**：C语言被广泛应用，因为它的仿真速度比传统的RTL（ Register Transfer Level）仿真快得多，同时提供了精确的定时和优化的硬件描述语言（Hardware Description Language，HDL）设计。 3. **预认证平台和组件级IP**：使用Xilinx提供的预认证平台、模块和组件级IP可以快速构建系统，节省设计时间和资源。 4. **高度自动化流程**：通过脚本化从设计验证到编程型FPGA的整个过程，实现了流程的自动化，减少了人为错误和重复工作。 5. **Vivado HLS设计流程更新**：2018.2版本的指南对Vivado High-Level Synthesis (HLS)设计流程进行了更新，确保用户能利用最新的工具和技术。 6. **版本历史**：文档记录了从2018.2到2018.3的修订历史，包括在2018.3版本中无变化的发布。 7. **内容结构**：指南分为多个章节，如系统设计、壳层开发和C语言IP开发，涵盖了设计方法论、系统架构划分、壳层设计验证以及C语言在IP开发中的应用等。通过学习和实践这份白皮书中的内容，设计者能够更有效地利用Xilinx Vivado工具进行高性能FPGA设计，提高生产率和产品质量。随着软件定义硬件（SDH）趋势的发展，C语言作为高级设计手段的使用将变得越来越重要。这份文档是设计师不可或缺的参考资料，对于那些寻求在现代FPGA设计领域保持竞争力的工程师来说，是提升技能和项目管理的关键资源。

UltraFast High-Level Productivity Design Methodology Guide 13

UG1197 (v2018.2) June 6, 2018 www.xilinx.com

Chapter 2: System Design

Key benefits of this methodology are:

• The shell is developed and verified independently of the rest of the design.

• Board-level integration and device pin planning are addressed by a separate dedicated

team working in parallel.

• The shell is saved and re-used (even re-edited), allowing multiple derivative designs to

be quickly realized.

• The differentiated logic is developed and verified independently of the shell.

• The pre-verified shell and differentiated logic are quickly integrated into a complete

system.

When partitioning your system, the first task is to determine what will be implemented in

the shell and what will be implemented as differentiated logic.

Shell Design

A shell design provides two key attributes to a high productivity methodology:

• Separating standard interface logic from the differentiated logic, allowing the

development and verification of both to proceed in parallel.

X-Ref Target - Figure 2-1

Figure 2-1: Shell Design Example

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UltraFast High-Level Productivity Design Methodology Guide 14

UG1197 (v2018.2) June 6, 2018 www.xilinx.com

Chapter 2: System Design

• Creating a re-usable design, or shell, that can be used to quickly create design

derivatives. A shell should ideally contain the parts of the design that are standard,

such as design interfaces and interface IP. However, a shell can also contain blocks used

for pre-processing or post-processing. If the processing functions are independent of

the core design IP, and if the processing functions could be used across multiple

designs, it is more ideal to place these blocks in the shell. The shell re-use

methodology allows blocks to be easily removed from the shell.

Irrespective of the logic you decide to incorporate into the shell design, a key attribute of

the shell design is that the internal interfaces, those which connect to the internal design IP,

should be implemented using standard interfaces. Use of standard internal interfaces such

as AXI will enhance the shell re-use by doing the following:

• Allowing the shell to be easily connected to a design IP that has yet to be developed

• Ensuring that verification of the shell also verifies the internal interfaces

• Enabling use of the high productivity integration features described in IP Integrator

and Standard Interfaces

Even if you are initially only thinking of one design, a shell based methodology allows you

to easily create derivative designs after the initial design is implemented.

More details about shell development and verification are described in Chapter 3, Shell

Development.

IP Design

The key feature of the IP development flow is that it includes only the IP that differentiates

the product from the shell.

The design IP is not standard and will be developed. Much of the development effort is

running simulations to validate that the design provides the correct functionality. This effort

can be minimized, and simulation run times improved, by not including standard blocks

that do not impact the new functionality being developed; those blocks should be in the

shell.

The figure below shows a representation of a complete system with design IP added to the

shell design. A key feature of the completed system is that it might contain IP developed

from many different sources, such as:

• IP generated from C/C++ using Vivado HLS

• IP generated from System Generator

•IP from RTL

• Xilinx

•Third-Party IP

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Xilinx Vivado UG1197：2018.2版的高效层次设计方法指南

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