UniIC_Techdoc, Rev. I 2023-04
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.5 Input / Output Signal Functional Description
Table 3 - Input / Output Signal Functional Description
Symbol
Type
Function
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK.
CKE
Input
Clock Enable: CKE High activates, and CKE Low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down ( active row in any bank).
CKE is asynchronous for Self-Refresh exit. After V
REFCA
and V
REFDQ
have become stable
during the power on and initialization sequence, they must be maintained during all operations
(including Self-Refresh). CKE must be maintained High throughout read and write accesses.
Input buffers, excluding CK, /CK, ODT, CKE and /RESET are disabled during Power-down.
Input buffers, excluding CKE and RESET are disabled during self refresh.
/CS
Input
Chip Select: All commands are masked when /CS is registered High. /CS provides for external
Rank selection on systems with multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
ODT
Input
On-Die Termination: ODT (registered High) enables termination resistance internal to the
DDR3L SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS and DM signal
for
×
8
configurations. The ODT signal will be ignored if the Mode Register MR1 is programmed
to disable ODT and during Self Refresh.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled High coincident with that input data during a Write access. DM is sampled on both
edges of DQS.
BA0 - BA2
Input
Bank Address Inputs: Define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines which mode register is to be accessed during a
mode register set cycle.
A0 – A15
Input
Address Inputs: Provides the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12 | /BC have additional functions, see below). The address inputs also provide
the op-code during Mode Register Set commands.
A10 | AP
Input
Auto-Precharge: A10 | AP is sampled during Read/Write commands to determine whether
Auto-Precharge should be performed to the accessed bank after the Read/Write operation.
(High: Auto-Precharge, Low: no Auto-Precharge). A10 | AP is sampled during Precharge
command to determine whether the Precharge applies to one bank (A10 Low) or all banks
(A10 High). If only one bank is to be precharged, the bank is selected by bank addresses.
A12 | /BC
Input
Burst Chop: A12 | /BC is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed. (High: no burst chop, Low: burst chopped). See
“Command Truth Table” on Page 11 for details.
DQ
Input/
Output
Data Input/Output: Bi-directional data bus.
DQS /DQS
Input/
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
in write data. The data strobes DQS are paired with differential signals /DQS, to provide
differential pair signaling to the system during both read and write. DDR3L
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