SCB13H4G160AF DDR3L SDRAM Data Sheet Rev.I (2023-04): Revision History & Features

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SCB13H4G160AF是一款4位 DDR3L SDRAM内存模块，其数据手册详细记录了产品的演变历史和规格信息。该内存于2017年12月首次发布，随着版本更新，它经历了多个关键改动，以满足不同的应用需求和工业标准。在2019年4月的B版本中，产品加入了对2133MHz速度的支持，提升了性能范围。同年10月的C版本对行地址格式进行了调整，确保了更高的兼容性和准确性。接下来的几个月，文档重点在于图形修正，如2020年6月的D和E版本分别修改了图1（512Mb×8组件的引脚布局）和图2（256Mb×16组件的引脚布局），以及更新了图片，以便用户能更清晰地了解产品结构。 2020年9月的F版本引入了工业级产品的选项，扩展了应用领域。2020年10月，图6的4GBit组件x8配置包装外形图进行了更新，进一步优化了设计细节。在2022年8月的H版本中，重要的 IDD5B1600 & 1866 参数值得到了修订，可能涉及功耗或温度特性方面的改进。最后一个重大改动发生在2023年4月的I版本，修正了一个错误，将1600MHz速度等级的CL-tRCD-tRP参数从9-9-9更改为11-11-11，这可能反映了时序设置的优化，以提高内存性能和稳定性。数据手册强调了对欧洲RoHS合规性的承诺，并鼓励用户提供反馈以持续改进产品的质量。如果有任何疑问或建议，用户可以直接发送电子邮件至info@unisemicon.com，以帮助制造商不断优化SCB13H4G160AF的数据手册，使其更加准确和用户友好。 SCB13H4G160AF数据手册不仅提供了产品的技术规格，还展示了其版本控制和不断完善的历程，这对于选择和使用这款内存芯片的工程师和技术人员来说，是至关重要的参考资源。

UniIC_Techdoc, Rev. I 2023-04

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Data Sheet

SCB13H4Gxx0AF

4-Gbit DDR3L SDRAM

1.5 Input / Output Signal Functional Description

Table 3 - Input / Output Signal Functional Description

Symbol

Type

Function

CK, /CK

Input

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK.

CKE

Input

Clock Enable: CKE High activates, and CKE Low deactivates internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self-Refresh operation (all banks idle), or Active Power-Down ( active row in any bank).

CKE is asynchronous for Self-Refresh exit. After V

REFCA

and V

REFDQ

have become stable

during the power on and initialization sequence, they must be maintained during all operations

(including Self-Refresh). CKE must be maintained High throughout read and write accesses.

Input buffers, excluding CK, /CK, ODT, CKE and /RESET are disabled during Power-down.

Input buffers, excluding CKE and RESET are disabled during self refresh.

/CS

Input

Chip Select: All commands are masked when /CS is registered High. /CS provides for external

Rank selection on systems with multiple ranks. /CS is considered part of the command code.

/RAS, /CAS, /WE

Input

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

ODT

Input

On-Die Termination: ODT (registered High) enables termination resistance internal to the

DDR3L SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS and DM signal

for

configurations. The ODT signal will be ignored if the Mode Register MR1 is programmed

to disable ODT and during Self Refresh.

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled High coincident with that input data during a Write access. DM is sampled on both

edges of DQS.

BA0 - BA2

Input

Bank Address Inputs: Define to which bank an Active, Read, Write or Precharge command is

being applied. Bank address also determines which mode register is to be accessed during a

mode register set cycle.

A0 – A15

Input

Address Inputs: Provides the row address for Active commands and the column address for

Read/Write commands to select one location out of the memory array in the respective bank.

(A10/AP and A12 | /BC have additional functions, see below). The address inputs also provide

the op-code during Mode Register Set commands.

A10 | AP

Input

Auto-Precharge: A10 | AP is sampled during Read/Write commands to determine whether

Auto-Precharge should be performed to the accessed bank after the Read/Write operation.

(High: Auto-Precharge, Low: no Auto-Precharge). A10 | AP is sampled during Precharge

command to determine whether the Precharge applies to one bank (A10 Low) or all banks

(A10 High). If only one bank is to be precharged, the bank is selected by bank addresses.

A12 | /BC

Input

Burst Chop: A12 | /BC is sampled during Read and Write commands to determine if burst

chop (on-the-fly) will be performed. (High: no burst chop, Low: burst chopped). See

“Command Truth Table” on Page 11 for details.

Input/

Output

Data Input/Output: Bi-directional data bus.

DQS /DQS

Input/

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered

in write data. The data strobes DQS are paired with differential signals /DQS, to provide

differential pair signaling to the system during both read and write. DDR3L

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