Delta-Sigma调制器理论与设计详解

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Delta-Sigma数据转换器理论、设计与模拟是电子工程领域的重要课题，特别是在微电子、通信和集成电路设计方面。这本由IEEE Press出版的权威书籍《Delta-Sigma调制器：理论、设计与模拟》深入探讨了这种调制技术的基本原理和实际应用。Delta-Sigma调制器是一种数字/模拟转换器（DAC）和模数转换器（ADC）的核心组成部分，它通过一种称为"多级量化噪声塑造"（Oversampling Noise Shaping）的技术，实现了高分辨率和低噪声性能。其工作原理基于时间积分，通过对输入信号进行多次采样并将其映射到有限数量的离散值，然后通过一个低通滤波器来恢复原始信号的连续特性。通过增加采样速率（即“超采样”），可以减少量化噪声的影响，从而实现更高的数据转换精度。这种技术特别适用于音频信号处理、视频编码以及对线性度和信噪比要求高的系统。书中详细介绍了Delta-Sigma调制器的设计方法，包括但不限于选择合适的调制阶数、优化滤波器设计、以及如何实施有效的数字信号处理算法。此外，还涉及到了实际的模拟电路实现、噪声分析以及系统仿真工具的应用，这些都是工程师在实际项目中必须掌握的关键技能。与本书类似的其他出版物，如《Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation》，由James C. Candy和Gabor C. Terne斯合作编著，提供了更深入的理论探讨和实践案例，适合进一步研究或作为参考教材。同时，关于时钟分配网络在VLSI电路和系统中的应用、非挥发性半导体存储器的技术、设计和应用等主题的书籍，也展现了电子工程领域的广泛性和交叉性。《Delta-Sigma Data Converters Theory, Design, and Simulation》是电子工程师和研究人员必备的一本书，无论是在理论理解还是实际应用上，都能提供丰富的学习资源，帮助读者提升在数据转换器设计领域的专业素养。

Preface

This

book

has the distinction

being the first original text on the subject

delta-sigma

data

conversion.

Because

this, we

thought

our

readers

might

appreciate a little back-

ground

how

this

book

came

into being. In 1992, the

IEEE

Press

approached

about

authoring a

book

on this subject. At the time, we felt that in

order

to do the

job

right, it

would be necessary to enlist a

number

authors

renowned

for their expertise in areas

related to

delta-sigma

modulation. After all, the field

delta-sigma

modulation

encom-

passes many diverse disciplines: systems and control theory, digital and analog signal

processing, VLSI integrated circuit design, and

knowledge

consumer

and cornmunica-

tions applications. We did not feel qualified by ourselves to write about all

these.

Therefore.

quickly

concluded

that we

should

gather

additional

experts

who

could

join

us in thoroughly

covering

these specialties and then treat the chapters more or less inde-

pendently. With this style

book, there is

always

a tendency for the authors to

overlap

material. hut we tried to orchestrate the overall effort to rninimize

overlap

and to maxi-

mizc original content. Nevertheless,

if the book

comes

across to the readers as a collection

of chapters, we

confess

that it really is

just

that

Nonetheless

hope

that this text is use-

ful and authoritative, and that it will quickly

become

a standard for both industry and aca-

dcmia

in this important area.

We are grateful to the

contributing

authors for their

excellent

material, and to the

reviewers (Professors Ian

Galton

and Stanley Lipshitz, Dr.

David

Rich, and others) for

their valuable

comments

and suggestions.

Steven R. Norsworthy

Richard Schreier

Gabor

C. Ternes

xviii Introduction

realizable. The delta modulator suppresses the low-frequency end of the signal spectrum,

which needs to be restored at the receiver end. This causes the dynamic range to decrease

with signal frequency and causes a cumulative error due to line noise.

It was proposed by Inose, Yasuda, and Murakami in 1962 [4] to add the loop filter to

the front end of a delta modulator and then move it inside the loop. For the simple case of

an integrator used as loop filter, the resulting system contained an integrator in the forward

path, followed by the (I-bit) quantizer, and the feedback loop contained only a I-bit digi-

tal-to-analog converter (DAC). Since this system contained a delta modulator and an inte-

grator, they named it a delta-sigma modulator, where the "sigma" denoted the summation

performed by the integrator. It was often called sigma-delta modulator by later workers.

Today, both names are in use. The output of the modulator contains the original input sig-

nal plus the first difference of the quantization error, as was the case for the error feedback

coder. Thus, both delta-sigma and error feedback coders are noise-shaping modulators.

They suppress the error in the baseband and thus achieve improved dynamic range across

this band independent of the signal frequency. The structure is free of the practical prob-

lems

the previous coders; the only component in the feedback loop is a l-bit DAC,

which can be made nearly ideal with careful design.

In the 34 years since its first description, the basic delta-sigma converter has been

modified many times and in many ways. The first important change was suggested in

1977 by Ritchie [5]. He proposed using several integrators in cascade in the forward path

to create a higher order loop filter, with each integrator receiving an additional input from

the DAC. The latter was needed to prevent instability. In an influential paper published in

1985 [6], Candy gave extensive design information on the double-integrator loop. Even

so, for more than two integrators in the loop, the stability was conditional and had to be

verified by numerical simulation. In 1987, Lee and Sodini gave design techniques for sta-

ble higher order loops [7, 8]. Based on these, delta-sigma ADCs with fourth- and

fifth-order loop filters containing several cascaded switched-capacitor (SC) integrators

and resonators have been successfully produced by several integrated circuit (IC) compa-

nies.

A different approach for the design of stable high-order delta-sigma ADCs was pro-

posed in 1986 by Hayashi et al. [9]. In their system (which they named MASH, for multi-

stage noise shaping) a single-integrator delta-sigma ADC processes the signal, and the

resulting large quantization error is converted by a second delta-sigma ADC into digital

data. The digital outputs of the two ADCs are combined through a digital stage that can-

cels the quantization error of the first ADC and differentiates the quantization error of the

second. The resulting digital signal contains a high-pass filtered replica of the quantization

error; the order of filtering is the sum of the orders of the two loop filters. To prevent the

leakage of unfiltered quantization noise to the output, the analog integrator in the first (sig-

nal) loop needs to function nearly ideally. This makes the practical realization somewhat

difficult. The principle can be extended to the realization of high-order converters, and

successful third- and fourth-order MASH ADCs have been reported.

Another way of enhancing the performance of a delta-sigma ADC is to use a multibit

internal quantizer. This, however, necessitates the inclusion of a multibit DAC in the feed-

back loop. The linearity of this DAC limits the linearity of the complete ADC, and hence

its design is a daunting task. Several techniques have been used to overcome this problem.

In 1989, Carley suggested the use of dynamic element matching to reduce the effect of

Introduction

xix

DAC nonlinearity on the overall response [I

also, Larson et al. [11] proposed the use of

digital correction to cancel it. In 1990, Leslie and Singh introduced an architecture that

used a single-bit DAC and a multibit ADC to achieve both good linearity and low quanti-

zation noise l l2]. Other dual-quantization techniques were also proposed, as well as tech-

niques that, instead of randomizing the noise due to the unavoidable nonlinearity error of

the multibit DAC, high-pass filtered it (see Chapter 8 of this book for details).

The development of delta-sigma DACs followed a similar path. Ritchie et al. [13]

proposed an interpolative DAC, based on an error feedback configuration, in 1974; in

1986, Candy and Huynh extended the concept to a second-order system, which used the

MASI-I

technique (proposed shortly before Hayashi et al.!) to combine the output signals

of two first-order digital loops

141.

A 16-bit single-loop second-order delta-sigma DAC,

using an error feedback topology, was described in 1987 by Naus et al. [15]. Higher order

loops have followed; in 1991, Sooch et al. described an I8-bit DAC using a fifth-order

loop filter

1161.

Several techniques were also offered for realizing delta-sigma DACs with

multibit internal DACs. Carley and Kenney

[171.

Schouwenaars et al. [18], and Xu et

£11.

[19] described such systems.

Recently, great interest has developed in bandpass delta-sigma converters that offer

efficient signal processing for digital wireless devices. The idea of constructing a delta-

sigma ADC tuned to a nonzero center frequency was first disclosed in 1987 [20] but was

independently reinvented a number of times [21-23]. Several realizations of bandpass

delta-sigma converters have been reported (see Chapter 9), with the most recent involving

the use of a sixth-order multistage (MASH) architecture to convert signals in the 3.25±0.1

MHz range with l l-bit accuracy [24]. All low-pass delta-sigma architectures (including

rnultibit systems and DACs) have their bandpass counterparts.

THEORY

(R.

SCHREIER)

Although it is possible to divine some intuitive feel for the operation of a delta-sigma

modulator from its behavior in the time domain, the easiest way to understand a delta-

sigma modulator is in tenus of the frequency-domain description of its "linear model." In

this model a nonlinear operation, quantization, is replaced by the addition of a noise sig-

nal. Linear system theory is then invoked to show that the output of the modulator is there-

fore the sum of the filtered input signal and the filtered quantization noise. The two

components can be filtered independently, under the control of the designer. This allows

delta-sigma modulators to separate spectrally the input signal from the noise introduced

by quantization. Subsequent digital filtering then removes the out-of-band noise, leaving

an accurate digital replica of the original analog input.

The understanding afforded by the linear model is sufficient to explain the most fun-

damental characteristic of a delta-sigma modulator, namely the shaping of quantization

noise. The linear model is also accurate enough to estimate the performance of a wide

variety of delta-sigma modulator architectures. Unfortunately, the linear model breaks

down when assumptions regarding the nature of the quantization noise, such as whiteness

or the possession of a particular probability density function, fail to hold [25]. Two nota-

ble instances of these failures of the linear model are the generation of idle-channel

tones and instability in the modulator. Tones result when the quantization noise contains

Introduction

discrete (or nearly discrete) spectral lines. Chapter 2 discusses the available theoretical

results regarding the nature of the quantization noise in a delta-sigma modulator, while

Chapter 3 deals with the practical resolution of the tone problem. Although the available

theory is unable to answer the question "How bad are the tones?," the techniques of

Chapter 3 are effective in eliminating idle-channel tones.

Stability is the second major unanswered theoretical question regarding delta-sigma

modulation. For a number of years it was believed that modulators of order 3 or more were

automatically unstable, but after Ritchie [5] and Lee [7] showed that high-order modula-

tors could in fact be stabilized, high-order designs proliferated. Unfortunately, those

designs were achieved through the application of ad hoc criteria (backed up by simulation

or the construction of a prototype) rather than a rigorous design methodology. Judging by

the fact that it took more than a decade for the stability of a second-order modulator to be

rigorously established, and even then only for a constant input [26], it is likely that the

question "Is my modulator stable?" will continue to be addressed by simulation and other

approximate methods well into the next millennium. Chapter 4 presents the available the-

oretical results and ad hoc methods so that new designers may construct high-order modu-

lators even though an iron-clad design methodology is not yet available.

APPLICATIONS

(S.

NORSWORTHY)

It took nearly three decades from the earliest works [1-4] on oversampled noise shaping

and delta modulation techniques until the introduction of high-volume commercial prod-

ucts that used these principles. Semiconductor technology simply did not reach very

large scale integrated (VLSI) proportions until the mid-1980s, and without the fine-line

complementary metal-oxide-semiconductor (CMOS), the digital filtering required in

delta-sigma converters for decimation and interpolation makes these circuits too expen-

sive.

Noise shaping and oversampling principles lend themselves most favorably to appli-

cations that require one or more of the following attributes: relatively low frequency

«100

kHz) and high resolution (>12 bits), high-complexity high-integration single-chip

designs using mixed analog and digital signal processing, and low-cost CMOS-only pro-

cessing. Certainly the delta-sigma technique has not completely supplanted more tradi-

tional data conversion techniques. Even at the time of this writing, there are architectural

techniques and designs that compete favorably with delta-sigma on the basis of cost and

power dissipation.

The first (and probably largest) application of delta-sigma conversion is in the field

of digital telephony. There are many subsets in this field with widely varying require-

ments. Voiceband codecs for the public switched telephone network require 13-bit linear

(8-bit companded) resolution and 8 ksamp/s conversion rates. Echo-canceling modems

such as CCITT V.32 and V.34 require 12-16-bit resolution and 8 ksamp/s rates. ISDN

(Integrated Services Digital Network) U-interface transceivers require 13-16-bit linear-

ity and 80-160-ksamp/s rates. Digital cellular telephones utilize delta-sigma both for voi-

ceband speech coding and for IF-to-baseband radio interface data conversion, such as I1Q

modulation and demodulation. Bandpass delta-sigma modulators (Chapter 9) are begin-

ning to be explored as alternatives to low-pass modulators for the IF-to-baseband inter-

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