MPC5200数据手册：高性能嵌入式处理器

需积分: 9 54 浏览量更新于2024-07-17 收藏 6.58MB PDF 举报

“MPC5200.pdf 是一份关于PowerPC系列微处理器MPC5200的数据手册，由Freescale Semiconductor（现为NXP半导体）发布。这份手册详细介绍了MPC5200的硬件特性、接口、外设功能等，并提供了最新的规格信息。MPC5200芯片集成了高性能的MPC603e系列G2_LE核心，专为通信和系统集成设计，其创新的BestComm I/O子系统可以隔离外围设备的常规维护任务，减轻核心处理器的负担。” MPC5200是基于PowerPC架构的微处理器，它具有以下主要特点： 1. **高性能核心**：采用MPC603e系列的G2_LE核心，提供强大的处理能力。 2. **BestComm I/O子系统**：这是一个创新设计，能够独立处理外围设备的功能，如中断管理，从而提高系统的效率和响应速度。 3. **内存控制器**：内置SDRAM/DDR内存控制器，支持高速存储器访问。 4. **外部总线接口**：提供灵活的外部总线接口，可连接各种外部设备。 5. **PCI控制器**：支持PCI（Peripheral Component Interconnect）总线，用于高速扩展其他硬件模块。 6. **USB和ATA接口**：集成USB控制器和ATA接口，满足数据传输需求。 7. **网络接口**：内置以太网控制器，实现网络连接。 8. **串行控制器**：包含六个可编程串行控制器（PSC），可用于UART、IrDA、Modem等多种串行通信协议。 9. **其他接口**：集成I2C、SPI、CAN、J1850等接口，支持多种工业标准通信协议。 10. **定时器和GPIO**：提供定时器和通用输入输出（GPIO）引脚，满足各种定时和控制需求。此外，数据手册还包括电气和热特性、封装信息、管脚配置、功耗分析以及编程和应用指南等内容，为软件开发人员提供详尽的技术参考。由于内容涉及众多硬件细节和接口规范，对于开发针对MPC5200的嵌入式系统或驱动程序的工程师来说，这份手册具有极高的参考价值。开发者可以通过访问Freescale Semiconductor（现NXP半导体）的官方网站获取最新的MPC5200产品概述页面，以获取最新的数据和更新信息。

Electrical and Thermal Characteristics

MPC5200 Data Sheet, Rev. 4

Freescale Semiconductor 13

There is a separate oscillator for the independent Real-Time Clock (RTC) system.

The MPC5200 clock generation uses two phase locked loop (PLL) blocks.

• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal

system clock. The system clock frequency is determined by the external reference frequency and

the settings of the SYS_PLL configuration.

• The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The

G2_LE core clock frequency is determined by the system clock frequency and the settings of the

CORE_PLL configuration.

3.2.1 System Oscillator Electrical Characteristics

3.2.2 RTC Oscillator Electrical Characteristics

3.2.3 System PLL Electrical Characteristics

Table 8. System Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

SYS_XTAL frequency f

sys_xtal

15.6 33.3 35.0 MHz O1.1

Oscillator start-up time t

up_osc

— — 100 µsO1.2

Table 9. RTC Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

RTC_XTAL frequency f

rtc_xtal

— 32.768 — kHz O2.1

Table 10. System PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

SYS_XTAL frequency f

sys_xtal

NOTES:

The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,

CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies.

15.6 33.3 35.0 MHz O3.1

SYS_XTAL cycle time T

sys_xtal

(1)

66.6 30.0 28.5 ns O3.2

SYS_XTAL clock input jitter t

jitter

This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different

types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but

the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the

operating frequency.

— — 150 ps O3.3

System VCO frequency f

VCOsys

(1)

250 533 800 MHz O3.4

System PLL relock time t

lock

Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

— — 100 µsO3.5

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor14

3.2.4 G2_LE Core PLL Electrical Characteristics

The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means

of a voltage-controlled core PLL.

3.3 AC Electrical Characteristics

Hyperlinks to the indicated timing specification sections are provided below.

AC Test Timing Conditions:

Unless otherwise noted, all test conditions are as follows:

Table 11. G2_LE PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

G2_LE frequency f

core

NOTES:

The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system

frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or

minimum operating frequencies.

50 — 550 MHz O4.1

G2_LE cycle time t

core

(1)

2.85 — 40.0 ns O4.2

G2_LE VCO frequency f

VCOcore

(1)

400 — 1200 MHz O4.3

G2_LE input clock frequency f

XLB_CLK

25 — 367 MHz O4.4

G2_LE input clock cycle time t

XLB_CLK

2.73 — 50.0 ns O4.5

G2_LE input clock jitter t

jitter

This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different

types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but

the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the

operating frequency.

— — 150 ps O4.6

G2_LE PLL relock time t

lock

Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

— — 100 µsO4.7

• AC Operating Frequency Data • USB

• Clock AC Specifications • SPI

•Resets •MSCAN

• External Interrupts • I

• SDRAM • J1850

•PCI •PSC

• Local Plus Bus • GPIOs and Timers

• ATA • IEEE 1149.1 (JTAG) AC Specifications

• Ethernet

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor16

3.3.3 Resets

The MPC5200 has three reset pins:

•PORRESET - Power on Reset

•HRESET - Hard Reset

•SRESET - Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt

trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC

Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.

Notes:

1. For PORRESET

the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards

its minimum pulse width equals the minimum given for HRESET

related to the same reference clock.

2. The t

VDD_stable

describes the time which is needed to get all power supplies stable.

3. For t

lock,

refer to the Oscillator/PLL section of this specification for further details.

4. For t

up_osc,

refer to the Oscillator/PLL section of this specification for further details.

5. Following the deassertion of PORRESET

, HRESET and SRESET remain low for 4096 reference clock cycles.

6. The deassertion of HRESET

for at least the minimum pulse width forces the internal resets to be active for an additional 4096

clock cycles.

NOTE

As long as VDD is not stable the HRESET

output is not stable.

Table 13. SYS_XTAL_IN Timing

Sym Description Min Max Units SpecID

CYCLE

SYS_XTAL_IN cycle time.

NOTES:

CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the

resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the

MPC5200 User Manual [1].

28.6 64.1 ns A2.1

RISE

SYS_XTAL_IN rise time. — 5.0 ns A2.2

FALL

SYS_XTAL_IN fall time. — 5.0 ns A2.3

DUTY

SYS_XTAL_IN duty cycle (measured at V

SYS_XTAL_IN duty cycle is measured at V

40.0 60.0 % A2.4

SYS_XTAL_IN input voltage high 2.0 — V A2.5

SYS_XTAL_IN input voltage low — 0.8 V A2.6

Table 14. Reset Pulse Width

Name Description Min Pulse Width

Max Pulse

Width

Reference Clock SpecID

PORRESET

Power On Reset t

VDD_stable

up_osc

lock

— SYS_XTAL_IN A3.1

HRESET

Hardware Reset 4 clock cycles — SYS_XTAL_IN A3.2

SRESET

Software Reset 4 clock cycles — SYS_XTAL_IN A3.3

剩余79页未读，继续阅读

qq_45190392

粉丝: 0
资源: 2

MPC5200数据手册：高性能嵌入式处理器

MPC5200B的技术手册

PowerPC5200BSamba开发板用户手册

MPC5200开发板原理demo

U-Boot Porting Guide MPC5200B.pdf

PID vs MPC.pdf

MPC560XPRM.pdf

MPC8308RM.pdf

MPC5744PRM.pdf

MPC5744P.pdf

MPC5643LRM.pdf

最新资源