5
DS90LV027A
www.ti.com
SNLS026D –MARCH 2000–REVISED JUNE 2016
Product Folder Links: DS90LV027A
Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except V
OD
.
(2) The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers
outputs.
(3) All typicals are given for: V
CC
= 3.3 V and T
A
= 25°C.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
(1)(2)
PARAMETER TEST CONDITIONS MIN TYP
(3)
MAX UNIT
V
OD
Output differential voltage R
L
= 100 Ω (see Figure 15), DO+, DO − pins 250 360 450 mV
ΔV
OD
V
OD
magnitude change R
L
= 100 Ω (see Figure 15), DO+, DO − pins 1 35 mV
V
OH
Output high voltage R
L
= 100 Ω (see Figure 15), DO+, DO − pins 1.4 1.6 V
V
OL
Output low voltage R
L
= 100 Ω (see Figure 15), DO+, DO − pins 0.9 1.1 V
V
OS
Offset voltage R
L
= 100 Ω (see Figure 15), DO+, DO − pins 1.125 1.2 1.375 V
ΔV
OS
Offset magnitude change R
L
= 100 Ω (see Figure 15), DO+, DO − pins 0 3 25 mV
I
OXD
Power-off leakage V
OUT
= V
CC
or GND, V
CC
= 0 V, DO+, DO− pins ±1 ±10 μA
I
OSD
Output short-circuit current DO+, DO− pins –5.7 –8 mA
V
IH
Input high voltage DI pin 2 V
CC
V
V
IL
Input low voltage DI pin GND 0.8 V
I
IH
Input high current V
IN
= 3.3 V or 2.4 V, DI pin ±2 ±10 μA
I
IL
Input low current V
IN
= GND or 0.5 V, DI pin ±1 ±10 μA
V
CL
Input clamp voltage I
CL
= −18 mA, DI pin –1.5 –0.6 V
I
CC
Power supply current V
IN
= V
CC
or GND, V
CC
pin
No load 8 14
mA
R
L
= 100 Ω 14 20
(1) These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage,
temperature) ranges.
(2) C
L
includes probe and fixture capacitance.
(3) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50 Ω, t
r
≤ 1 ns, t
f
≤ 1 ns (10%-90%).
(4) All typicals are given for: V
CC
= 3.3 V and T
A
= 25°C.
(5) t
SKD1
, |t
PHLD
− t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) t
SKD2
is the Differential Channel to Channel Skew of any event on the same device.
(7) t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same V
CC
and within 5°C of each other within the operating temperature range.
(8) t
SKD4
, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min|
differential propagation delay.
(9) f
MAX
generator input conditions: t
r
= t
f
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
V
OD
> 250 mV, all channels switching.
6.6 Switching Characteristics
R
L
= 100 Ω and C
L
= 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)
(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP
(4)
MAX UNIT
t
PHLD
Differential propagation delay high to low 0.3 0.8 1.5 ns
t
PLHD
Differential propagation delay low to high 0.3 1.1 1.5 ns
t
SKD1
Differential pulse skew |t
PHLD
− t
PLHD
|
(5)
0 0.3 0.7 ns
t
SKD2
Channel to channel skew
(6)
0 0.4 0.8 ns
t
SKD3
Differential part to part skew
(7)
0 1 ns
t
SKD4
Differential part to part skew
(8)
0 1.2 ns
t
TLH
Transition low to high time 0.2 0.5 1 ns
t
THL
Transition high to low time 0.2 0.5 1 ns
f
MAX
Maximum operating frequency
(9)
350 MHz
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