5
DS90LV011AH
www.ti.com.cn
ZHCSJ91B –SEPTEMBER 2005–REVISED JANUARY 2019
Copyright © 2005–2019, Texas Instruments Incorporated
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except V
OD
.
(2) All typicals are given for: V
DD
= +3.3V and T
A
= +25°C.
(3) The DS90LV011AH is a current mode device and only function with datasheet specification when a resistive load is applied to the
drivers outputs.
(4) Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
6.5 Electrical Characteristics
over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)(2)(3)
PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT
|V
OD
| Output Differential Voltage
R
L
= 100 Ω
(Figure 7 and Figure 8)
OUT+,
OUT−
250 350 450 mV
ΔV
OD
V
OD
Magnitude Change 3 35 mV
V
OS
Offset Voltage
R
L
= 100 Ω
(Figure 7)
1.125 1.22 1.375 V
ΔV
OS
Offset Magnitude Change 0 1 25 mV
I
OFF
Power-off Leakage V
OUT
= 3.6 V or GND, V
DD
= 0 V ±1 ±10 μA
I
OS
Output Short Circuit Current
(4)
V
OUT+
and V
OUT−
= 0 V −6 −24 mA
I
OSD
Differential Output Short Circuit
Current
(4)
V
OD
= 0 V −5 −12 mA
C
OUT
Output Capacitance 3 pF
V
IH
Input High Voltage
TTL IN
2 V
DD
V
V
IL
Input Low Voltage GND 0.8 V
I
IH
Input High Current V
IN
= 3.3 V or 2.4 V ±2 ±10 μA
I
IL
Input Low Current V
IN
= GND or 0.5 V ±1 ±10 μA
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 −0.6 V
C
IN
Input Capacitance 3 pF
I
DD
Power Supply Current
No Load
V
IN
= V
DD
or GND V
DD
5 8 mA
R
L
= 100 Ω 7 10 mA
(1) All typicals are given for: V
DD
= +3.3V and T
A
= +25°C.
(2) These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(3) C
L
includes probe and fixture capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
r
≤ 1 ns, t
f
≤ 1 ns (10%-90%).
(5) t
SKD1
, |t
PHLD
− t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(6) t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same V
DD
and within 5°C of each other within the operating temperature range.
(7) t
SKD4
, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min|
differential propagation delay.
(8) f
MAX
generator input conditions: t
r
= t
f
< 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, V
OD
>
250mV. The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the
transitions times (t
TLH
and t
THL
).
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified.
(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHLD
Differential Propagation Delay High to Low
R
L
= 100Ω, C
L
= 15 pF
(Figure 9 and Figure 10)
0.3 1 1.5 ns
t
PLHD
Differential Propagation Delay Low to High 0.3 1.1 1.5 ns
t
SKD1
Differential Pulse Skew |t
PHLD
− t
PLHD
|
(5)
0 0.1 0.7 ns
t
SKD3
Differential Part to Part Skew
(6)
0 0.2 1 ns
t
SKD4
Differential Part to Part Skew
(7)
0 0.4 1.2 ns
t
TLH
Transition Low to High Time 0.2 0.5 1 ns
t
THL
Transition High to Low Time 0.2 0.5 1 ns
f
MAX
Maximum Operating Frequency
(8)
200 250 MHz
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