AT45DB081B的SPI驱动程序设计：5V单片机数据接收与内存编程

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本文档主要介绍了如何使用AVR微控制器编写AT45DB081B驱动程序，这是一种专为5V系统设计、支持串行接口的8兆位非易失性闪存存储器。AT45DB081B具有独特的特点和功能，包括： 1. **电源兼容性**：单个4.5V至5.5V供电，适用于对电源需求较为灵活的应用。 2. **串行接口架构**：通过Serial Peripheral Interface (SPI)模式0和3实现数据通信，提供了高效和便捷的接口连接。 3. **编程操作**： - **快速编程**：一次周期内即可完成擦除和编程，典型时间为7毫秒。 - **页面大小与数量**：4096个页面，每个页面包含264字节，总内存容量为8,650,752位。 4. **数据缓冲**：有两个264字节的内部数据缓冲区，允许在主存储器页面重新编程的同时接收数据，增强了实时性和效率。 5. **定时器与控制**：内置程序和控制定时器，可能用于管理操作流程和超时。 6. **低功耗设计**： - **活动读取电流**：典型情况下，读取电流仅为15毫安，有利于延长电池寿命。 - **待机电流**：仅10微安的典型CMOS待机电流，对于节能应用极为关键。 7. **频率限制**：最大工作频率可达10MHz，确保了高速数据传输的能力。 8. **硬件保护**：具备硬件数据保护功能，提高了数据的安全性。 9. **输入输出兼容**：CMOS和TTL兼容的输入输出接口，适应多种电路环境。 10. **温度范围**：商业和工业级温度范围，确保在不同环境下的可靠运行。编写AT45DB081B驱动程序时，开发人员需要关注以下几个步骤： - 初始化SPI通信：设置适当的时钟速度和模式，以及设备地址。 - 设置缓冲区：配置buffer1和buffer2的地址，以及 datasave_buff数组的位置和大小。 - 数据传输：根据具体应用，选择从buffer1或buffer2向datasave_buff数组读取指定数量的数据，可能涉及分页处理。 - 控制程序定时器：如果存在，确保在执行数据传输的同时，定时器可以正确管理操作的顺序。 - 功耗管理：在不使用时，确保进入低功耗模式以节省电力。 - 错误处理与异常处理：考虑到数据传输的可靠性，应包括错误检测和处理机制。这篇文档是针对AVR平台开发人员的一份实用指南，提供了驱动AT45DB081B非易失性闪存的具体方法，包括硬件接口配置、数据传输策略以及性能优化等关键知识点。

AT45D081

Buffer to Main Memory Page Program with Built-In Erase.

A page of data is first transferred from the main memory to

buffer 1 or buffer 2, and then the same data (from buffer 1

or buffer 2) is programmed back into its original page of

main memory. An 8-bit opcode, 58H for buffer 1 or 59H for

buffer 2, is followed by the three reserved bits, 12 address

bits (PA11-PA0) that specify the page in main memory to

be rewritten, and nine additional don't care bits. When a

low to high transition occurs on the CS

pin, the part will first

transfer data from the page in main memory to a buffer and

then program the data from the buffer back into same page

of main memory. The operation is internally self-timed and

should take place in a maximum time of t

. During this

time, the status register will indicate that the part is busy.

If the main memory is programmed or reprogrammed

sequentially page by page, then the programming algo-

rithm shown in Figure 1 is recommended. Otherwise, if

multiple bytes in a page or several pages are programmed

randomly in the main memory, then the programming algo-

rithm shown in Figure 2 is recommended.

STATUS REGISTER:

The status register can be used to

determine the device’s ready/busy status, the result of a

Main Memory Page to Buffer Compare operation, or the

device density. To read the status register, an opcode of

57H must be loaded into the device. After the last bit of the

opcode is shifted in, the eight bits of the status register,

starting with the MSB (bit 7), will be shifted out on the SO

pin during the next eight clock cycles. The five most-signifi-

cant bits of the status register will contain device informa-

tion, while the remaining three least-significant bits are

reserved for future use and will have undefined values.

After bit 0 of the status register has been shifted out, the

sequence will repeat itself (as long as CS

remains low and

SCK is being toggled) starting again with bit 7. The data in

the status register is constantly updated, so each repeating

sequence will output new data.

Ready/busy status is indicated using bit 7 of the status reg-

ister. If bit 7 is a 1, then the device is not busy and is ready

to accept the next command. If bit 7 is a 0, then the device

is in a busy state. The user can continuously poll bit 7 of the

status register by stopping SCK once bit 7 has been output.

The status of bit 7 will continue to be output on the SO pin,

and once the device is no longer busy, the state of SO will

change from 0 to 1. There are six operations which can

cause the device to be in a busy state: Main Memory Page

to Buffer Transfer, Main Memory Page to Buffer Compare,

Buffer to Main Memory Page Program with Built-In Erase,

Buffer to Main Memory Page Program without Built-In

Erase, Main Memory Page Program, and Auto Page

Rewrite.

The result of the most recent Main Memory Page to Buffer

Compare operation is indicated using bit 6 of the status

page matches the data in the buffer. If bit 6 is a 1, then at

least one bit of the data in the main memory page does not

match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the

status register. For the AT45D081, the three bits are 1, 0,

and 0. The decimal value of these three binary bits does

not equate to the device density; the three bits represent a

combinational code relating to differing densities of Serial

DataFlash devices, allowing a total of eight different density

configurations.

Read/Program Mode Summary

The modes listed above can be separated into two groups

— modes which make use of the flash memory array

(Group A) and modes which do not make use of the flash

memory array (Group B).

Group A modes consist of:

1. Main memory page read

2. Main memory page to buffer 1 (or 2) transfer

3. Main memory page to buffer 1 (or 2) compare

4. Buffer 1 (or 2) to main memory page program with

built-in erase

5. Buffer 1 (or 2) to main memory page program with-

out built-in erase

6. Main memory page program

7. Auto page rewrite

Group B modes consist of:

1. Buffer 1 (or 2) read

2. Buffer 1 (or 2) write

3. Status read

If a Group A mode is in progress (not fully completed) then

another mode in Group A should not be started. However,

during this time in which a Group A mode is in progress,

modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually

accommodate a continuous data stream. While data is

being programmed into main memory from buffer 1, data

can be loaded into buffer 2 (or vice versa). See application

note AN-4 (“Using Atmel’s Serial DataFlash”) for more

details.

Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RDY/BUSY

COMP 1 0 0 X X X

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