PCIe 4.0规格详解：新一代数据传输标准

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PCIE SPEC 4.0 规格书是PCI Express (PCIe) 的最新标准，于2014年2月19日发布，它是PCI Express技术的第四个主要版本，旨在提供更快的数据传输速率和增强的功能。PCIe是一种广泛应用于计算机系统中的高速接口标准，用于连接各种设备，如显卡、网卡、硬盘控制器等。在PCIe 4.0规范中，相较于前一代，它引入了显著的进步。首先，数据传输速率提升至5.0 GT/s（Gigatransfer per second），这意味着数据传输速度有了翻倍的提升，能够支持更高效的数据交换。此外，规格书还包含了对先前版本中批准的错误修正（Errata）和工程更改（ECNs）的整合，确保了系统的稳定性与兼容性。修订历史记录显示，从初始版本1.0到4.0，标准经历了多次迭代，每一次修订都吸收了之前发现的问题和改进意见，如内部错误报告、多播支持、原子操作、可扩展的内存条功能（Resizable BAR）、动态功率分配、基于ID的排序控制、延迟容忍度报告、替代路由标识符解释、扩展标签启用默认设置、TLP处理提示等。这些功能不仅增强了PCIe的性能，还提高了系统的灵活性和能效。值得注意的是，PCIe 4.0还考虑到了电源管理的优化，如动态功率分配，这有助于在保证性能的同时，降低设备的功耗。同时，对ID为基础的排序（ID-Based Ordering）的更新，使得设备间的通信更加有序，减少了数据包冲突的可能性。对于开发者和硬件制造商来说，PCIe 4.0规格书提供了详细的规范，包括信号时序、带宽需求、错误检测与恢复机制，以及如何实现新功能的硬件设计指南。遵循这个标准，他们可以确保产品与当前市场上的其他设备无缝协作，并保持向未来的升级路径开放。 PCIe SPEC 4.0 是一项关键的技术文档，对于理解现代计算机系统内部通信架构、优化高性能计算应用和提升整个IT基础设施的性能至关重要。随着技术的发展，后续的规格更新将继续推动PCIe标准的进步，适应不断增长的数据处理需求。

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 49

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 50

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 54

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 56

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 57

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 62

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 65

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 66

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 67

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 68

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 73

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 75

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 75

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 77

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 78

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 79

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 81

FIGURE 2-13: TRANSACTION ID .................................................................................................... 82

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 84

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 88

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 88

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 89

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 90

FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 91

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 91

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 92

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 93

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 93

FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 95

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 105

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 106

FIGURE 2-27: LN MESSAGE ......................................................................................................... 108

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 109

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 111

FIGURE 2-30: LTR MESSAGE ...................................................................................................... 112

FIGURE 2-31: OBFF MESSAGE ................................................................................................... 113

FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 114

FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 115

FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 116

FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 117

FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 117

FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 124

FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 126

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3

FIGURE 2-39: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 131

FIGURE 2-40: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 148

FIGURE 2-41: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 148

FIGURE 2-42: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 151

FIGURE 2-43: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 152

FIGURE 2-44: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION ........................................................................................................................ 168

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 176

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 179

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED

FRAMING ............................................................................................................................. 184

FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 185

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 187

FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 187

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 187

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 188

FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 188

FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 188

FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 189

FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 190

FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS

............................................................................................................................................. 192

FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 194

FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 202

FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 203

FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 207

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 213

FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 214

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 215

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 215

FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 218

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 219

FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 219

FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 220

FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 220

FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL ............................................................... 222

FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A

BLOCK ................................................................................................................................. 223

FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 223

FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 227

FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 229

FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 229

FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 230

FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 230

FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 238

FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 240

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3

FIGURE 4-20: 8.0 GT/S EQUALIZATION FLOW ............................................................................. 248

FIGURE 4-21: 16.0 GT/S EQUALIZATION FLOW ........................................................................... 249

FIGURE 4-22: ELECTRICAL IDLE EXIT ORDERED SET FOR 8.0 GT/S AND ABOVE DATA RATES ... 260

FIGURE 4-23: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 275

FIGURE 4-24: DETECT SUBSTATE MACHINE ............................................................................... 277

FIGURE 4-25: POLLING SUBSTATE MACHINE .............................................................................. 286

FIGURE 4-26: CONFIGURATION SUBSTATE MACHINE .................................................................. 301

FIGURE 4-27: RECOVERY SUBSTATE MACHINE ........................................................................... 325

FIGURE 4-28: L0S SUBSTATE MACHINE ...................................................................................... 332

FIGURE 4-29: L1 SUBSTATE MACHINE ........................................................................................ 334

FIGURE 4-30: L2 SUBSTATE MACHINE ........................................................................................ 336

FIGURE 4-31: LOOPBACK SUBSTATE MACHINE ........................................................................... 341

FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 357

FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 365

FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT ........................ 368

FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING . 371

FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE .................................................. 375

FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED) ................ 388

FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 389

FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 391

FIGURE 5-9: STATE DIAGRAM FOR L1 PM SUBSTATES ................................................................ 397

FIGURE 5-10: DOWNSTREAM PORT WITH A SINGLE PLL ............................................................. 398

FIGURE 5-11: MULTIPLE DOWNSTREAM PORTS WITH A SHARED PLL ......................................... 399

FIGURE 5-12: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 401

FIGURE 5-13: EXAMPLE: L1.1 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 402

FIGURE 5-14: L1.2 SUBSTATES .................................................................................................... 403

FIGURE 5-15: EXAMPLE: ILLUSTRATION OF BOUNDARY CONDITION DUE TO DIFFERENT SAMPLING

CLKREQ# ...................................................................................................................... 404

FIGURE 5-16: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING UPSTREAM PORT INITIATED EXIT ... 406

FIGURE 5-17: EXAMPLE: L1.2 WAVEFORMS ILLUSTRATING DOWNSTREAM PORT INITIATED EXIT

............................................................................................................................................. 406

FIGURE 6-1: ERROR CLASSIFICATION .......................................................................................... 416

FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING

OPERATIONS ........................................................................................................................ 433

FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 434

FIGURE 6-4: TC FILTERING EXAMPLE ......................................................................................... 454

FIGURE 6-5: TC TO VC MAPPING EXAMPLE ............................................................................... 455

FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS .................. 456

FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH ................ 457

FIGURE 6-8: SWITCH ARBITRATION STRUCTURE ......................................................................... 458

FIGURE 6-9: VC ID AND PRIORITY ORDER – AN EXAMPLE ......................................................... 459

FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL .............................................................. 462

FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 496

FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS ................................ 497

FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES ............................................... 510

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3

FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE ......................................... 512

FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES ................................................... 530

FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 534

FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT .................................................. 535

FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS ...................................................... 537

FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY

MESSAGES ........................................................................................................................... 538

FIGURE 6-20. PASID TLP PREFIX: ....................................................................................... 541

FIGURE 6-21: SAMPLE SYSTEM BLOCK DIAGRAM ....................................................................... 545

FIGURE 6-22: LN PROTOCOL BASIC OPERATION ......................................................................... 546

FIGURE 6-23: EXAMPLE SYSTEM TOPOLOGIES USING PTM ......................................................... 552

FIGURE 6-24: PRECISION TIME MEASUREMENT LINK PROTOCOL ................................................ 553

FIGURE 6-25: PRECISION TIME MEASUREMENT EXAMPLE ........................................................... 555

FIGURE 6-26: PTM REQUESTER OPERATION ............................................................................... 558

FIGURE 6-27: PTM TIMESTAMP CAPTURE EXAMPLE ................................................................... 561

FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 566

FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 566

FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 567

FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER ............................................................ 578

FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER ................................................................ 585

FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER ................................................................ 587

FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ..................................................... 591

FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER .............................................. 592

FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 593

FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE ................................................................. 595

FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 595

FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 596

FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 598

FIGURE 7-14: DEVICE CONTROL REGISTER ................................................................................. 603

FIGURE 7-15: DEVICE STATUS REGISTER .................................................................................... 610

FIGURE 7-16: LINK CAPABILITIES REGISTER ............................................................................... 612

FIGURE 7-17: LINK CONTROL REGISTER ..................................................................................... 617

FIGURE 7-18: LINK STATUS REGISTER ........................................................................................ 626

FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 629

FIGURE 7-20: SLOT CONTROL REGISTER ..................................................................................... 631

FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 635

FIGURE 7-22: ROOT CONTROL REGISTER .................................................................................... 637

FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 638

FIGURE 7-24: ROOT STATUS REGISTER ....................................................................................... 639

FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER ........................................................................ 640

FIGURE 7-26: DEVICE CONTROL 2 REGISTER .............................................................................. 646

FIGURE 7-27: LINK CAPABILITIES 2 REGISTER ............................................................................ 650

FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 653

FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 658

FIGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT .................................. 663

FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 664

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3

FIGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE

............................................................................................................................................. 666

FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER ........................ 667

FIGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER ........................................................ 668

FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER ........................................................... 670

FIGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER ..................................................... 672

FIGURE 7-37: CORRECTABLE ERROR STATUS REGISTER ............................................................. 674

FIGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 675

FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 676

FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 678

FIGURE 7-41: ROOT ERROR COMMAND REGISTER ...................................................................... 678

FIGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 680

FIGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 682

FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 683

FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 684

FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 685

FIGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 686

FIGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 687

FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 688

FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 689

FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER .................................................................. 690

FIGURE 7-52: VC RESOURCE CONTROL REGISTER ...................................................................... 692

FIGURE 7-53: VC RESOURCE STATUS REGISTER ......................................................................... 694

FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES ........................................... 696

FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES

............................................................................................................................................. 697

FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE ......................... 698

FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER .................................. 699

FIGURE 7-58: SERIAL NUMBER REGISTER ................................................................................... 700

FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 701

FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER ............... 702

FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 703

FIGURE 7-62: LINK ENTRY .......................................................................................................... 704

FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 704

FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0 .......................................................................... 706

FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1 .......................................................................... 707

FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY ...................................... 708

FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER ...................... 708

FIGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 709

FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 713

FIGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER .............................................................. 714

FIGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE ................................. 715

FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER .......................................... 716

FIGURE 7-73: POWER BUDGETING DATA REGISTER .................................................................... 717

FIGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 719

FIGURE 7-75: ACS EXTENDED CAPABILITY ................................................................................ 720

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