PCIe 4.0规格详解：新一代数据传输标准
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更新于2024-07-20
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收藏 11.74MB PDF 举报 PCIE SPEC 4.0 规格书是PCI Express (PCIe) 的最新标准，于2014年2月19日发布，它是PCI Express技术的第四个主要版本，旨在提供更快的数据传输速率和增强的功能。PCIe是一种广泛应用于计算机系统中的高速接口标准，用于连接各种设备，如显卡、网卡、硬盘控制器等。
在PCIe 4.0规范中，相较于前一代，它引入了显著的进步。首先，数据传输速率提升至5.0 GT/s（Gigatransfer per second），这意味着数据传输速度有了翻倍的提升，能够支持更高效的数据交换。此外，规格书还包含了对先前版本中批准的错误修正（Errata）和工程更改（ECNs）的整合，确保了系统的稳定性与兼容性。
修订历史记录显示，从初始版本1.0到4.0，标准经历了多次迭代，每一次修订都吸收了之前发现的问题和改进意见，如内部错误报告、多播支持、原子操作、可扩展的内存条功能（Resizable BAR）、动态功率分配、基于ID的排序控制、延迟容忍度报告、替代路由标识符解释、扩展标签启用默认设置、TLP处理提示等。这些功能不仅增强了PCIe的性能，还提高了系统的灵活性和能效。
值得注意的是，PCIe 4.0还考虑到了电源管理的优化，如动态功率分配，这有助于在保证性能的同时，降低设备的功耗。同时，对ID为基础的排序（ID-Based Ordering）的更新，使得设备间的通信更加有序，减少了数据包冲突的可能性。
对于开发者和硬件制造商来说，PCIe 4.0规格书提供了详细的规范，包括信号时序、带宽需求、错误检测与恢复机制，以及如何实现新功能的硬件设计指南。遵循这个标准，他们可以确保产品与当前市场上的其他设备无缝协作，并保持向未来的升级路径开放。
PCIe SPEC 4.0 是一项关键的技术文档，对于理解现代计算机系统内部通信架构、优化高性能计算应用和提升整个IT基础设施的性能至关重要。随着技术的发展，后续的规格更新将继续推动PCIe标准的进步，适应不断增长的数据处理需求。
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
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Figures
FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 49
FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 50
FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 54
FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 56
FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 57
FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 62
FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 65
FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 66
FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 67
FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 68
FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 73
FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 75
FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 75
FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 77
FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 78
FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 79
FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 81
FIGURE 2-13: TRANSACTION ID .................................................................................................... 82
FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 84
FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 88
FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 88
FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 89
FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 90
FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 91
FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 91
FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 92
FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 93
FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 93
FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 95
FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 105
FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 106
FIGURE 2-27: LN MESSAGE ......................................................................................................... 108
FIGURE 2-28: DRS MESSAGE ...................................................................................................... 109
FIGURE 2-29: FRS MESSAGE ...................................................................................................... 111
FIGURE 2-30: LTR MESSAGE ...................................................................................................... 112
FIGURE 2-31: OBFF MESSAGE ................................................................................................... 113
FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 114
FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 115
FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 116
FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 117
FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 117
FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 124
FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 126
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