AT45DB041B：2.5V-3.6V单电源SPI闪存芯片

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"45DB041B是一款专为各种数字语音、图像、程序代码和数据存储应用设计的串行接口闪存芯片。它在2.5伏或2.7伏电压下工作，内存容量为4,325,376位，组织结构为2048个264字节的页面。该芯片还包含两个264字节的SRAM数据缓冲区，允许在主存储器重新编程时接收数据。支持单周期重编程（擦除和编程）、页编程和块擦除操作，并具有连续读取功能、低功耗特性以及硬件数据保护功能。该芯片与AT45DB041和AT45DB041A完全兼容，输入引脚具有5.0伏耐受能力，适用于商业和工业温度范围。" 45DB041B闪存芯片是Atmel公司推出的一款高性能存储解决方案，其主要特点包括： 1. **电源兼容性**：芯片支持2.5伏到3.6伏或2.7伏到3.6伏的电压范围，确保了在不同电源环境下的稳定工作。 2. **SPI接口**：采用串行外设接口（SPI），最高时钟频率可达20MHz，这使得该芯片能够快速高效地进行数据传输。 3. **高效编程**：提供页编程操作，单次循环即可完成擦除和编程，极大地提高了编程速度。共有2048个264字节的页面，总计约1MB的存储空间。 4. **块擦除操作**：除了页编程，芯片还支持块擦除操作，这对于大量数据的处理非常有用。 5. **SRAM数据缓冲区**：内置两个264字节的SRAM数据缓冲区，允许在对非易失性存储器进行编程时接收新数据，实现了数据处理的并行性。 6. **连续读取能力**：通过整个数组实现连续读取，提高了读取效率，特别是在需要连续访问大量数据的应用中。 7. **低功耗设计**：在活动状态下，读取电流典型值仅为4mA，待机状态下的CMOS电流典型值仅为2µA，这对于电池供电或者对能耗有严格要求的设备特别有利。 8. **硬件数据保护**：芯片内置硬件数据保护机制，保障存储在其中的数据安全。 9. **兼容性**：与前代产品AT45DB041和AT45DB041A完全兼容，方便升级和替换。 10. **输入耐压**：SI、SCK、CS、RESET和WPP引脚均能承受5.0伏的电压，增加了系统设计的灵活性。 11. **温度范围**：支持商业和工业标准的温度范围，确保在不同环境下都能可靠工作。这款芯片广泛应用于需要大容量、高速读写和低功耗的嵌入式系统，如移动设备、智能家电、工业控制、物联网设备和各种数据记录系统。其高效能和可靠性使其成为各种数据存储应用的理想选择。

AT45DB041B

1938F–DFLSH–10/02

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A

previously erased page within main memory can be programmed with the contents of

either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or

89H for buffer 2, must be followed by the four reserved bits, 11 address bits

(PA10 - PA0) that specify the page in the main memory to be written, and nine addi-

tional don’t care bits. When a low-to-high transition occurs on the CS

pin, the part will

program the data stored in the buffer into the specified page in the main memory. It is

necessary that the page in main memory that is being programmed has been previously

erased. The programming of the page is internally self-timed and should take place in a

maximum time of t

. During this time, the status register will indicate that the part is

busy.

Successive page programming operations without doing a page erase are not recom-

mended. In other words, changing bytes within a page from a “1” to a “0” during multiple

page programming operations without erasing that page is not recommended.

PAGE ERASE: The optional Page Erase command can be used to individually erase

any page in the main memory array allowing the Buffer to Main Memory Page Program

without Built-in Erase command to be utilized at a later time. To perform a Page Erase,

an opcode of 81H must be loaded into the device, followed by four reserved bits,

11 address bits (PA10 - PA0), and nine don’t care bits. The 11 address bits are used to

specify which page of the memory array is to be erased. When a low-to-high transition

occurs on the CS

pin, the part will erase the selected page to 1s. The erase operation is

internally self-timed and should take place in a maximum time of t

. During this time,

the status register will indicate that the part is busy.

BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer

to Main Memory Page Program without Built-in Erase command to be utilized to reduce

programming times when writing large amounts of data to the device. To perform a

Block Erase, an opcode of 50H must be loaded into the device, followed by four

reserved bits, eight address bits (PA10 - PA3), and 12 don’t care bits. The eight address

bits are used to specify which block of eight pages is to be erased. When a low-to-high

transition occurs on the CS

pin, the part will erase the selected block of eight pages to

1s. The erase operation is internally self-timed and should take place in a maximum

time of t

. During this time, the status register will indicate that the part is busy.

Block Erase Addressing

PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block

0 0000000XXX 0

0 0000001XXX 1

0 0000010XXX 2

0 0000011XXX 3

•

1 1111100XXX252

1 1111101XXX253

1 1111110XXX254

1 1111111XXX255

AT45DB041B

1938F–DFLSH–10/02

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-

tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase

operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-

grammed into a specified page in the main memory. To initiate the operation, an 8-bit

opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the four reserved bits

and 20 address bits. The 11 most significant address bits (PA10 - PA0) select the page

in the main memory where data is to be written, and the next nine address bits

(BFA8 - BFA0) select the first byte in the buffer to be written. After all address bits are

shifted in, the part will take data from the SI pin and store it in one of the data buffers. If

the end of the buffer is reached, the device will wrap around back to the beginning of the

buffer. When there is a low-to-high transition on the CS

pin, the part will first erase the

selected page in main memory to all 1s and then program the data stored in the buffer

into the specified page in the main memory. Both the erase and the programming of the

page are internally self-timed and should take place in a maximum of time t

. During

this time, the status register will indicate that the part is busy.

Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred

from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit

opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the four reserved

bits, 11 address bits (PA10 - PA0) which specify the page in main memory that is to be

transferred, and nine don’t care bits. The CS

pin must be low while toggling the SCK pin

to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer

of the page of data from the main memory to the buffer will begin when the CS

pin tran-

sitions from a low to a high state. During the transfer of a page of data (t

XFR

), the status

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can

be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,

60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of

the four reserved bits, 11 address bits (PA10 - PA0) which specify the page in the main

memory that is to be compared to the buffer, and nine don’t care bits. The CS

pin must

be low while toggling the SCK pin to load the opcode, the address bits, and the don’t

care bits from the SI pin. On the low-to-high transition of the CS

pin, the 264 bytes in the

selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2.

During this time (t

XFR

), the status register will indicate that the part is busy. On comple-

tion of the compare operation, bit 6 of the status register is updated with the result of the

compare.

AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or

multiple pages of data are modified in a random fashion. This mode is a combination of

two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page

Program with Built-in Erase. A page of data is first transferred from the main memory to

buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed

back into its original page of main memory. To start the rewrite operation, an 8-bit

opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the four reserved bits,

11 address bits (PA10 - PA0) that specify the page in main memory to be rewritten, and

nine additional don’t care bits. When a low-to-high transition occurs on the CS

pin, the

part will first transfer data from the page in main memory to a buffer and then program

the data from the buffer back into same page of main memory. The operation is inter-

nally self-timed and should take place in a maximum time of t

. During this time, the

status register will indicate that the part is busy.

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