Microchip 24CW160: High-Speed I2C EEPROM with Data Protection

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"Microchip-24CW160.pdf 是一份关于Microchip Technology Inc.推出的24CW系列EEPROM存储器的详细资料，主要涵盖了24CW160、24CW320和24CW640等不同容量的器件。这份文档是初步版，提供设备选择表、特性介绍、接口规格、电源范围、功耗信息以及封装选项等内容。" 24CW16X/24CW32X/24CW64X系列是Microchip公司推出的一系列EEPROM（电可擦可编程只读存储器）器件，主要特点包括： 1. 存储容量：这系列器件提供了16Kbit、32Kbit和64Kbit的不同选择，内部组织为单个2048x8bit、4096x8bit或8192x8bit的存储块，支持字节或页面写入，最大可达32字节，并可在同一块内进行字节或顺序读取。 2. 高速I2C接口：遵循工业标准，支持1MHz、400kHz和100kHz的传输速率。接口还具备输出斜率控制，减少地线反弹，以及施密特触发输入以抑制噪声。 3. 可编程硬件从机地址位：通过硬件地址寄存器（HAR）可以配置器件的从机地址，增加了系统的灵活性。 4. 多样的数据保护选项：提供软件写保护功能，通过写保护寄存器（WPR）实现，确保数据安全。 5. 宽泛的电源电压范围：工作电压在1.6V到5.5V之间，适合各种应用需求。 6. 低功耗CMOS技术：在5.5V电源下，写入电流最大为1.0mA，1MHz时读取电流同样为1.0mA；待机状态下电流仅为1μA，显著降低了系统功耗。 7. 高可靠性：该系列EEPROM具有超过一百万次的擦写周期，数据保留时间超过200年，同时提供4000V以上的静电放电保护，保证了器件在恶劣环境下的稳定工作。 8. 封装选项：包括8引脚SOIC、8引脚TSSOP、8引脚UDFN、5引脚SOT-23以及两种4球CSP封装，满足不同设计需求。 Microchip的24CW系列EEPROM是针对需要高可靠性和低功耗存储解决方案的应用而设计的，适用于工业自动化、物联网设备、嵌入式系统等多种场合。其丰富的功能和灵活的配置选项使得它能够适应多种多样的应用场景。

 2017 Microchip Technology Inc. Preliminary DS20005772A-page 9

24CW16X/24CW32X/24CW64X

TABLE 3-2: DEVICE PRESET SLAVE

ADDRESS

3.3.1.2 Read/Write Select Bit

The eighth bit (bit 0) of the device address byte is the

Read/Write Select (R/W

) bit. A read operation is

initiated if this bit is a logic ‘1’ and a write operation is

initiated if this bit is a logic ‘0’.

Upon the successful comparison of the device address

byte, the 24CW Series will respond. If a valid compari-

son is not made, the device will not respond and return

to a standby state.

3.3.2 WORD ADDRESS BYTES

Two 8-bit word address bytes are transmitted to the

device immediately following the device address byte.

The first word address byte contains the Most Signifi-

cant bits (MSbs) of the memory array word address to

specify which location in the EEPROM to start reading

or writing. Note that the number of word address bits

depends on the density.

When accessing the memory array, it is required that

bit 7 of the word address byte be set to a logic ‘0’.

When accessing the Configuration registers, it is

required that bit 7 of the first word address byte be set

to a logic ‘1’. Refer to Table 3-3 for details.

Next, the second word address byte is sent to the device

which provides the remaining eight bits of the word

address (A7 through A0). Refer to Ta ble 3- 4 for details.

TABLE 3-3: FIRST WORD ADDRESS BYTE

TABLE 3-4: SECOND WORD ADDRESS BYTE

Part Number Series

24CWXXX

Hardware Slave

Address Bits

A2 A1 A0

24CWXX0

(1)

000

24CWXX1

(1,2)

001

24CWXX2

(1,2)

010

24CWXX3

(1,2)

011

24CWXX4

(1,2)

100

24CWXX5

(1,2)

101

24CWXX6

(1,2)

110

24CWXX7

(1,2)

111

Note 1: ‘XX’ in the part number varies depending

on the density.

2: Contact your local sales representative for

hardware slave address availability.

Memory Region Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16-Kbit EEPROM 0xxxxA10 A9 A8

32-Kbit EEPROM 0xxxA11 A10 A9 A8

64-Kbit EEPROM 0xxA12 A11 A10 A9 A8

Configuration Registers 1xxxxxxx

Memory Region Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0

32-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0

64-Kbit EEPROM A7 A6 A5 A4 A3 A2 A1 A0

Configuration Registers

(1)

xxxxxxxx

Note 1: When accessing the Configuration registers, the second word address byte must be transmitted to the

device despite containing only don’t care values.

24CW16X/24CW32X/24CW64X

DS20005772A-page 10 Preliminary  2017 Microchip Technology Inc.

4.0 FUNCTIONAL DESCRIPTION

The 24CW Series supports a bidirectional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The bus must be

controlled by a master which generates the Serial

Clock (SCL), controls the bus access and generates

the Start and Stop conditions, while the 24CW Series

works as a slave. Both master and slave can operate

as a transmitter or receiver, but the master determines

which mode is activated.

5.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 5-1).

5.1 Bus Not Busy (A)

Both data and clock lines remain high.

5.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

5.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

5.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master.

5.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master must generate an extra clock

pulse, which is associated with this Acknowledge bit.

See Figure 5-2 for Acknowledge timing.

A device that Acknowledges must pull down the SDA

line during the Acknowledge clock pulse, in such a way,

that the SDA line is stable low during the high period of

the Acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During read

operations, the master must signal an end of data to the

slave by NOT generating an Acknowledge (NACK) bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24CW Series) will leave the data

line high to enable the master to generate the Stop

condition.

FIGURE 5-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24CW Series does not generate

any Acknowledge bits if an internal

programming cycle is in progress.

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

Start

Condition

SCL

SDA

(A) (B) (D) (D) (C) (A)

 2017 Microchip Technology Inc. Preliminary DS20005772A-page 11

24CW16X/24CW32X/24CW64X

FIGURE 5-2: ACKNOWLEDGE TIMING

5.6 Standby Mode

The 24CW Series features a low-power Standby mode

which is enabled when any one of the following occurs:

• A valid power-up sequence is performed (see

Section 1.1 “Power-up Requirements and

Reset Behavior”).

• A Stop condition is received by the device unless

it initiates an internal write cycle (see Section 6.0

“Write Operations”).

• At the completion of an internal write cycle (see

Section 6.0 “Write Operations”).

• An unsuccessful match of the Device Type Identi-

fier or hardware slave address in the device

address byte occurs (see Section 3.3 “Device

Addressing”).

• The master does not Acknowledge the receipt of

data read out from the device; instead, it sends a

NACK response.(see Section 7.0 “Read

Operations”).

5.7 Software Reset

After an interruption in protocol, power loss or system

Reset, any 2-wire device can be protocol reset by

clocking SCL until SDA is released by the EEPROM

and goes high. The number of clock cycles until SDA is

released by the EEPROM will vary. The Software Reset

sequence should not take more than nine dummy clock

cycles. Note that the Software Reset sequence will not

interrupt the internal write cycle and only resets the I

interface.

Once the Software Reset sequence is complete, new

protocol can be sent to the device by sending a Start

condition, followed by the protocol. Figure 5-3

illustrates the Software Reset sequence.

In the event that the device is still non-responsive, or

remains active on the SDA bus, a power cycle must be

used to reset the device (see Section 1.1.1 “Device

Reset”).

FIGURE 5-3: SOFTWARE RESET

SCL

987654321123

Transmitter must release the SDA line at this point,

allowing the receiver to pull the SDA line low, to

Acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point so the transmitter can

continue sending data.

Data from Transmitter

SDA

Acknowledge

Bit

Data from Transmitter

Dummy Clock Cycles

12389

SCL

SDA

SDA Released

by EEPROM

Device is

Software Reset

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