MAX II EPM1270 CPLD的JTAG与内系统编程特性

4星 · 超过85%的资源需积分: 10 73 浏览量更新于2024-12-14 收藏 117KB PDF 举报

"本文档是关于Altera Corporation的EPM1270PD型号CPLD（复杂可编程逻辑器件）的详细说明，主要关注该器件的JTAG（Joint Test Action Group）接口和在系统编程功能。EPM1270PD支持IEEE Std.1149.1标准的边界扫描测试，这是一种用于检测和修复硬件故障的方法，可以在电源完全接通且配置时间过后进行。JTAG端口允许用户利用Quartus II软件、Jam Standard Test and Programming Language（STAPL）文件或Jam Byte-Code文件进行编程，这对于现场升级和调试非常有用。 JTAG引脚支持1.5V、1.8V、2.5V和3.3V的不同电压等级，其兼容性由存储器银行的供电电压VCCIO决定，而在所有MAXII设备中，这些专用的JTAG引脚位于Bank1内。文档还列出了EPM1270PD支持的JTAG指令集，如表3-1所示，这部分包括了如SAMPLE/PRELOAD这样的基本操作，用于数据采集和预加载，以及其他高级调试和编程功能。在使用EPM1270PD时，开发者需确保在合适的电压环境下工作，并了解如何通过JTAG接口执行有效的测试和编程操作，这对于保证设计的正确实现和优化性能至关重要。对于那些需要进行复杂嵌入式系统设计和调试的工程师来说，这份文档提供了宝贵的参考资料，使得他们能够充分利用EPM1270PD的JTAG特性来简化开发流程和提高效率。"

Altera Corporation Core Version a.b.c variable 3–1

June 2004 Preliminary

Chapter 3. JTAG & In-System

Programmability

IEEE Std. 1149.1

(JTAG) Boundary

Scan Support

All MAX

II devices provide Joint Test Action Group (JTAG) boundary-

scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001

specification. JTAG boundary-scan testing can only be performed at any

time after V

CCINT

and all V

CCIO

banks have been fully powered and a

CONFIG

amount of time has passed. MAX II devices can also use the JTAG

port for in-system programming together with either the Quartus

software or hardware using Programming Object Files (.pof), Jam

Standard Test and Programming Language (STAPL) Files (.jam) or Jam

Byte-Code Files (.jbc).

The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The

supported voltage level and standard is determined by the V

CCIO

of the

bank where it resides. The dedicated JTAG pins reside in Bank 1 of all

MAX II devices.

MAX II devices support the JTAG instructions shown in Table 3–1.

Table 3–1. MAX II JTAG Instructions (Part 1 of 2)

JTAG Instruction Instruction Code Description

SAMPLE/PRELOAD 00 0000 0101 Allows a snapshot of signals at the device pins to be captured

and examined during normal device operation, and permits an

initial data pattern to be output at the device pins.

EXTEST (1) 00 0000 1111 Allows the external circuitry and board-level interconnects to

be tested by forcing a test pattern at the output pins and

capturing test results at the input pins.

BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO

pins, which allows the boundary scan test data to pass

synchronously through selected devices to adjacent devices

during normal device operation.

USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between

the TDI and TDO pins, allowing the USERCODE to be serially

shifted out of TDO. This register defaults to all 1’s if not

specified in the Quartus II software.

IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and

TDO, allowing the IDCODE to be serially shifted out of TDO.

MII51003-1.1

下载后可阅读完整内容，剩余9页未读，立即下载

mrsany

粉丝: 0
资源: 3

MAX II EPM1270 CPLD的JTAG与内系统编程特性

EPM1270-TQFP144.7z

EPM1270原理图

PWM.rar_EPM1270_EPM1270 PWM_fpga PWM _vhdl epm1270_基于FPGA+PWM

epm1270t256 pcb 封装

EPM1270-f256

epm1270光电传感器数据采集板protel 99se硬件设计原理图+pcb+bom文件.zip

epm1270t144c5n管脚图

用EPM1270T144C5设计两组交通灯的fpga代码

找一下 EPM HFM 的API说明文档

最新资源