TMS320F2803x技术手册：详细指南和重要信息（29页）

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TMS320F2803x技术手册是一份关于TMS320F2803x微控制器的技术参考手册。该手册涵盖了该微控制器的技术规格、功能特性、引脚描述、寄存器配置、以及应用举例等内容。该手册的编写旨在帮助工程师和技术人员了解和应用TMS320F2803x微控制器，以便设计和开发各种嵌入式系统和控制器。 TMS320F2803x微控制器是德州仪器公司（TI）推出的一款高性能、低功耗的数字信号控制器（DSC）。它采用了32位CPU核，并集成了丰富的外设和功能模块，包括模拟-数字转换模块（ADC）、PWM输出、通信接口（如SPI、SCI等）、时钟模块、以及多种定时器等。TMS320F2803x微控制器广泛应用于工业控制、电力电子、汽车电子、可再生能源等领域，以其强大的计算能力和丰富的外设配置受到了广大工程师和设计师的青睐。本手册包含了TMS320F2803x系列微控制器的完整数据手册和技术规格书，旨在为工程师和设计师提供全面的技术信息和参考资料。手册的前言部分介绍了本手册的组织结构和内容安排，以及使用本手册的一些注意事项，帮助读者更好地理解和使用本手册。接下来的章节分别介绍了TMS320F2803x微控制器的概述、引脚描述、功能特性、寄存器配置、电气特性、以及应用举例等内容。每一章节都包含了详细的技术说明和丰富的应用案例，帮助读者全面了解和掌握TMS320F2803x微控制器的特性和应用方法。总的来说，TMS320F2803x技术手册是一份非常重要的技术资料，对于正在设计和开发基于TMS320F2803x微控制器的系统的工程师和设计师来说，它提供了全面而深入的参考资料和技术指导。通过学习和应用本手册的内容，读者可以更好地理解和掌握TMS320F2803x微控制器的特性和应用方法，从而更好地完成其系统设计和开发工作。希望本手册能够对广大的工程师和设计师有所帮助，促进他们在嵌入式系统和控制器领域的技术创新和应用实践。

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Figure 7-13. eQEP Position-compare Event Generation Points..............................................................................................463

Figure 7-14. eQEP Position-compare Sync Output Pulse Stretcher....................................................................................... 463

Figure 7-15. eQEP Edge Capture Unit.................................................................................................................................... 465

Figure 7-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...................................................466

Figure 7-17. eQEP Edge Capture Unit - Timing Details.......................................................................................................... 466

Figure 7-18. eQEP Watchdog Timer........................................................................................................................................468

Figure 7-19. eQEP Unit Timer Base........................................................................................................................................ 468

Figure 7-20. eQEP Interrupt Generation..................................................................................................................................469

Figure 7-21. QPOSCNT Register............................................................................................................................................ 472

Figure 7-22. QPOSINIT Register.............................................................................................................................................473

Figure 7-23. QPOSMAX Register............................................................................................................................................474

Figure 7-24. QPOSCMP Register............................................................................................................................................475

Figure 7-25. QPOSILAT Register............................................................................................................................................ 476

Figure 7-26. QPOSSLAT Register...........................................................................................................................................477

Figure 7-27. QPOSLAT Register............................................................................................................................................. 478

Figure 7-28. QUTMR Register.................................................................................................................................................479

Figure 7-29. QUPRD Register................................................................................................................................................. 480

Figure 7-30. QWDTMR Register..............................................................................................................................................481

Figure 7-31. QWDPRD Register..............................................................................................................................................482

Figure 7-32. QDECCTL Register.............................................................................................................................................483

Figure 7-33. QEPCTL Register................................................................................................................................................485

Figure 7-34. QCAPCTL Register............................................................................................................................................. 488

Figure 7-35. QPOSCTL Register.............................................................................................................................................489

Figure 7-36. QEINT Register................................................................................................................................................... 490

Figure 7-37. QFLG Register.................................................................................................................................................... 492

Figure 7-38. QCLR Register.................................................................................................................................................... 494

Figure 7-39. QFRC Register....................................................................................................................................................496

Figure 7-40. QEPSTS Register............................................................................................................................................... 498

Figure 7-41. QCTMR Register.................................................................................................................................................500

Figure 7-42. QCPRD Register................................................................................................................................................. 501

Figure 7-43. QCTMRLAT Register...........................................................................................................................................502

Figure 7-44. QCPRDLAT Register...........................................................................................................................................503

Figure 8-1. ADC Block Diagram.............................................................................................................................................. 508

Figure 8-2. SOC Block Diagram.............................................................................................................................................. 509

Figure 8-3. ADCINx Input Model..............................................................................................................................................511

Figure 8-4. ONESHOT Single Conversion.............................................................................................................................. 515

Figure 8-5. Round Robin Priority Example.............................................................................................................................. 517

Figure 8-6. High Priority Example............................................................................................................................................518

Figure 8-7. Interrupt Structure................................................................................................................................................. 520

Figure 8-8. Timing Example For Sequential Mode / Late Interrupt Pulse................................................................................ 523

Figure 8-9. Timing Example For Sequential Mode / Early Interrupt Pulse...............................................................................524

Figure 8-10. Timing Example For Simultaneous Mode / Late Interrupt Pulse......................................................................... 525

Figure 8-11. Timing Example For Simultaneous Mode / Early Interrupt Pulse........................................................................ 526

Figure 8-12. Timing Example for NONOVERLAP Mode..........................................................................................................527

Figure 8-13. Temperature Sensor Transfer Function...............................................................................................................528

Figure 8-14. ADC Control Register 1 (ADCCTL1)................................................................................................................... 531

Figure 8-15. ADC Control Register 2 (ADCCTL2)................................................................................................................... 533

Figure 8-16. ADC Interrupt Flag Register (ADCINTFLG)........................................................................................................ 534

Figure 8-17. ADC Interrupt Flag Clear Register (ADCINTFLGCLR)....................................................................................... 535

Figure 8-18. ADC Interrupt Overflow Register (ADCINTOVF).................................................................................................536

Figure 8-19. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR)................................................................................537

Figure 8-20. Interrupt Select 1 and 2 Register (INTSEL1N2).................................................................................................. 538

Figure 8-21. Interrupt Select 3 and 4 Register (INTSEL3N4).................................................................................................. 538

Figure 8-22. Interrupt Select 5 and 6 Register (INTSEL5N6).................................................................................................. 538

Figure 8-23. Interrupt Select 7 and 8 Register (INTSEL7N8).................................................................................................. 539

Figure 8-24. Interrupt Select 9 and 10 Register (INTSEL9N10).............................................................................................. 539

Figure 8-25. ADC Start of Conversion Priority Control Register (SOCPRICTL)......................................................................541

Figure 8-26. ADC Sample Mode Register (ADCSAMPLEMODE)...........................................................................................543

Figure 8-27. ADC Interrupt Trigger SOC Select 1 Register (ADCINTSOCSEL1)....................................................................545

Figure 8-28. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2)....................................................................545

Figure 8-29. ADC SOC Flag 1 Register (ADCSOCFLG1).......................................................................................................546

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Figure 8-30. ADC SOC Force 1 Register (ADCSOCFRC1).................................................................................................... 547

Figure 8-31. ADC SOC Overflow 1 Register (ADCSOCOVF1)............................................................................................... 548

Figure 8-32. ADC SOC Overflow Clear 1 Register (ADCSOCOVFCLR1).............................................................................. 548

Figure 8-33. ADC SOC0-SOC15 Control Registers (ADCSOCxCTL).....................................................................................549

Figure 8-34. ADC Reference/Gain Trim Register (ADCREFTRIM)......................................................................................... 552

Figure 8-35. ADC Offset Trim Register (ADCOFFTRIM).........................................................................................................552

Figure 8-36. Comparator Hysteresis Control Register (COMPHYSTCTL).............................................................................. 553

Figure 8-37. ADC Revision Register (ADCREV)..................................................................................................................... 554

Figure 8-38. ADC RESULT0-RESULT15 Registers (ADCRESULTx)......................................................................................554

Figure 9-1. Comparator Block Diagram................................................................................................................................... 556

Figure 9-2. Comparator........................................................................................................................................................... 557

Figure 9-3. Ramp Generator Block Diagram........................................................................................................................... 558

Figure 9-4. Ramp Generator Behavior.................................................................................................................................... 559

Figure 9-5. Comparator Control (COMPCTL) Register........................................................................................................... 561

Figure 9-6. Compare Output Status (COMPSTS) Register..................................................................................................... 562

Figure 9-7. DAC Control (DACCTL) Register.......................................................................................................................... 562

Figure 9-8. DAC Value (DACVAL) Register.............................................................................................................................563

Figure 9-9. Ramp Generator Maximum Reference Active (RAMPMAXREF_ACTIVE) Register............................................ 563

Figure 9-10. Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register......................................... 563

Figure 9-11. Ramp Generator Decrement Value Active (RAMPDECVAL_ACTIVE) Register................................................. 564

Figure 9-12. Ramp Generator Decrement Value Shadow (RAMPDECVAL_SHDW) Register................................................564

Figure 9-13. Ramp Generator Status (RAMPSTS) Register................................................................................................... 564

Figure 10-1. CLA (Type 0) Block Diagram...............................................................................................................................567

Figure 10-2. Task Interrupt Vector (MVECT1/2/3/4/5/6/7/8) Register...................................................................................... 705

Figure 10-3. Control Register (MCTL)..................................................................................................................................... 706

Figure 10-4. Memory Configuration Register (MMEMCFG).................................................................................................... 707

Figure 10-5. CLA Peripheral Interrupt Source Select 1 Register (MPISRCSEL1)...................................................................708

Figure 10-6. Interrupt Flag Register (MIFR)............................................................................................................................ 709

Figure 10-7. Interrupt Overflow Flag Register (MIOVF)...........................................................................................................710

Figure 10-8. Interrupt Force Register (MIFRC)........................................................................................................................712

Figure 10-9. Interrupt Flag Clear Register (MICLR)................................................................................................................ 713

Figure 10-10. Interrupt Overflow Flag Clear Register (MICLROVF)........................................................................................714

Figure 10-11. Interrupt Enable Register (MIER)...................................................................................................................... 715

Figure 10-12. Interrupt Run Status Register (MIRUN).............................................................................................................716

Figure 10-13. Program Counter (MPC)................................................................................................................................... 717

Figure 10-14. CLA Status Register (MSTF).............................................................................................................................717

Figure 11-1. SPI CPU Interface............................................................................................................................................... 723

Figure 11-2. SPI Interrupt Flags and Enable Logic Generation............................................................................................... 726

Figure 11-3. SPI Master/Slave Connection..............................................................................................................................727

Figure 11-4. Serial Peripheral Interface Block Diagram...........................................................................................................728

Figure 11-5. SPICLK Signal Options........................................................................................................................................732

Figure 11-6. SPI: SPICLK-LSPCLK Characteristic When (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1....................733

Figure 11-7. SPI 3-wire Master Mode...................................................................................................................................... 734

Figure 11-8. SPI 3-wire Slave Mode........................................................................................................................................ 735

Figure 11-9. Five Bits per Character........................................................................................................................................737

Figure 11-10. SPI Digital Audio Receiver Configuration Using Two SPIs................................................................................739

Figure 11-11. Standard Right-Justified Digital Audio Data Format.......................................................................................... 740

Figure 11-12. SPI Configuration Control Register (SPICCR)...................................................................................................742

Figure 11-13. SPI Operation Control (SPICTL) Register......................................................................................................... 745

Figure 11-14. SPI Status (SPISTS) Register........................................................................................................................... 747

Figure 11-15. SPI Baud Rate Register (SPIBRR)....................................................................................................................749

Figure 11-16. SPI Emulation Buffer (SPIRXEMU) Register.....................................................................................................750

Figure 11-17. SPI Serial Input Buffer (SPIRXBUF) Register................................................................................................... 751

Figure 11-18. SPI Serial Output Buffer (SPITXBUF) Register.................................................................................................751

Figure 11-19. SPI Serial Data (SPIDAT) Register....................................................................................................................752

Figure 11-20. SPI FIFO Transmit (SPIFFTX) Register............................................................................................................ 753

Figure 11-21. SPI FIFO Receive (SPIFFRX) Register.............................................................................................................755

Figure 11-22. SPI FIFO Control (SPIFFCT) Register.............................................................................................................. 757

Figure 11-23. SPI Priority Control (SPIPRI) Register...............................................................................................................758

Figure 12-1. SCI CPU Interface...............................................................................................................................................762

Figure 12-2. Serial Communications Interface (SCI) Module Block Diagram..........................................................................764

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TMS320F2803x Microcontrollers 17

Figure 12-3. Typical SCI Data Frame Formats........................................................................................................................ 765

Figure 12-4. Idle-Line Multiprocessor Communication Format................................................................................................767

Figure 12-5. Double-Buffered WUT and TXSHF..................................................................................................................... 768

Figure 12-6. Address-Bit Multiprocessor Communication Format........................................................................................... 769

Figure 12-7. SCI Asynchronous Communications Format...................................................................................................... 770

Figure 12-8. SCI RX Signals in Communication Modes.......................................................................................................... 770

Figure 12-9. SCI TX Signals in Communications Mode.......................................................................................................... 771

Figure 12-10. SCI FIFO Interrupt Flags and Enable Logic...................................................................................................... 774

Figure 12-11. SCI Communications Control Register (SCICCR).............................................................................................778

Figure 12-12. SCI Control Register 1 (SCICTL1).................................................................................................................... 780

Figure 12-13. SCI Baud Rate (high) (SCIHBAUD) Register....................................................................................................782

Figure 12-14. SCI Baud Rate (low) (SCILBAUD) Register......................................................................................................783

Figure 12-15. SCI Control Register 2 (SCICTL2).................................................................................................................... 783

Figure 12-16. SCI Receive Status (SCIRXST) Register..........................................................................................................785

Figure 12-17. SCI Receive Emulation Buffer (SCIRXEMU) Register...................................................................................... 787

Figure 12-18. SCI Receive Data Buffer (SCIRXBUF) Register............................................................................................... 788

Figure 12-19. SCI Transmit Data Buffer (SCITXBUF) Register...............................................................................................789

Figure 12-20. SCI FIFO Transmit (SCIFFTX) Register............................................................................................................789

Figure 12-21. SCI FIFO Receive (SCIFFRX) Register............................................................................................................ 791

Figure 12-22. SCI FIFO Control (SCIFFCT) Register..............................................................................................................793

Figure 12-23. SCI Priority Control (SCIPRI) Register..............................................................................................................794

Figure 13-1. Multiple I2C Modules Connected........................................................................................................................ 796

Figure 13-2. I2C Module Conceptual Block Diagram.............................................................................................................. 799

Figure 13-3. Clocking Diagram for the I2C Module................................................................................................................. 799

Figure 13-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)..................................................................................800

Figure 13-5. Bit Transfer on the I2C bus..................................................................................................................................801

Figure 13-6. I2C Slave TX / RX Flowchart...............................................................................................................................803

Figure 13-7. I2C Master TX / RX Flowchart.............................................................................................................................804

Figure 13-8. I2C Module START and STOP Conditions..........................................................................................................805

Figure 13-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)........................................... 807

Figure 13-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)................................................................ 807

Figure 13-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)...............................................................808

Figure 13-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)........................................................................................808

Figure 13-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)..............................................................809

Figure 13-14. Synchronization of Two I2C Clock Generators During Arbitration.....................................................................809

Figure 13-15. Arbitration Procedure Between Two Master-Transmitters.................................................................................810

Figure 13-16. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.......................................................811

Figure 13-17. Enable Paths of the I2C Interrupt Requests......................................................................................................814

Figure 13-18. I2C FIFO Interrupt............................................................................................................................................. 815

Figure 13-19. I2C Own Address Register (I2COAR)............................................................................................................... 818

Figure 13-20. I2C Interrupt Enable Register (I2CIER).............................................................................................................819

Figure 13-21. I2C Status Register (I2CSTR)........................................................................................................................... 820

Figure 13-22. I2C Clock Low-time Divider (I2CCLKL) Register...............................................................................................824

Figure 13-23. I2C Clock High-time Divider (I2CCLKH) Register............................................................................................. 824

Figure 13-24. I2C Data Count (I2CCNT) Register...................................................................................................................825

Figure 13-25. I2C Data Receive Register (I2CDRR)............................................................................................................... 826

Figure 13-26. I2C Slave Address Register (I2CSAR)..............................................................................................................827

Figure 13-27. I2C Data Transmit Register (I2CDXR).............................................................................................................. 828

Figure 13-28. I2C Mode Register (I2CMDR)........................................................................................................................... 829

Figure 13-29. I2C Interrupt Source (I2CISRC) Register.......................................................................................................... 833

Figure 13-30. I2C Extended Mode Register (I2CEMDR).........................................................................................................834

Figure 13-31. I2C Prescaler (I2CPSC) Register......................................................................................................................835

Figure 13-32. I2C FIFO Transmit (I2CFFTX) Register............................................................................................................ 836

Figure 13-33. I2C FIFO Receive (I2CFFRX) Register.............................................................................................................838

Figure 14-1. eCAN Block Diagram and Interface Circuit......................................................................................................... 841

Figure 14-2. CAN Data Frame.................................................................................................................................................842

Figure 14-3. Architecture of the eCAN Module........................................................................................................................843

Figure 14-4. eCAN-A Memory Map......................................................................................................................................... 846

Figure 14-5. Initialization Sequence........................................................................................................................................ 851

Figure 14-6. CAN Bit Timing.................................................................................................................................................... 852

Figure 14-7. Interrupts Scheme............................................................................................................................................... 859

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Figure 14-8. Local-Acceptance-Mask Register (LAMn)...........................................................................................................865

Figure 14-9. Mailbox-Enable Register (CANME).....................................................................................................................866

Figure 14-10. Mailbox-Direction Register (CANMD)................................................................................................................866

Figure 14-11. Transmission-Request Set Register (CANTRS)................................................................................................867

Figure 14-12. Transmission-Request-Reset Register (CANTRR)........................................................................................... 868

Figure 14-13. Transmission-Acknowledge Register (CANTA).................................................................................................868

Figure 14-14. Abort-Acknowledge Register (CANAA)............................................................................................................. 869

Figure 14-15. Received-Message-Pending Register (CANRMP)............................................................................................869

Figure 14-16. Received-Message-Lost Register (CANRML)...................................................................................................870

Figure 14-17. Remote-Frame-Pending Register (CANRFP)................................................................................................... 870

Figure 14-18. Global Acceptance Mask Register (CANGAM)................................................................................................. 872

Figure 14-19. Master Control Register (CANMC)....................................................................................................................873

Figure 14-20. Bit-Timing Configuration Register (CANBTC)................................................................................................... 876

Figure 14-21. Error and Status Register (CANES).................................................................................................................. 878

Figure 14-22. Transmit-Error-Counter Register (CANTEC).....................................................................................................880

Figure 14-23. Receive-Error-Counter Register (CANREC)..................................................................................................... 880

Figure 14-24. Global Interrupt Flag 0 Register (CANGIF0)..................................................................................................... 882

Figure 14-25. Global Interrupt Flag 1 Register (CANGIF1)..................................................................................................... 882

Figure 14-26. Global Interrupt Mask Register (CANGIM)........................................................................................................884

Figure 14-27. Mailbox Interrupt Mask Register (CANMIM)......................................................................................................885

Figure 14-28. Mailbox Interrupt Level Register (CANMIL).......................................................................................................886

Figure 14-29. Overwrite Protection Control Register (CANOPC)............................................................................................ 886

Figure 14-30. TX I/O Control Register (CANTIOC)................................................................................................................. 887

Figure 14-31. RX I/O Control Register (CANRIOC).................................................................................................................887

Figure 14-32. Time-Stamp Counter Register (CANTSC).........................................................................................................888

Figure 14-33. Message-Object Time-Out Registers (MOTO).................................................................................................. 889

Figure 14-34. Message-Object Time Stamp Registers (MOTS).............................................................................................. 889

Figure 14-35. Time-Out Control Register (CANTOC).............................................................................................................. 890

Figure 14-36. Time-Out Status Register (CANTOS)................................................................................................................890

Figure 14-37. Message Identifier Register (MSGID) Register................................................................................................. 891

Figure 14-38. Message-Control Register (MSGCTRL)............................................................................................................893

Figure 14-39. Message-Data-Low Register With DBO = 0 (CANMDL)................................................................................... 894

Figure 14-40. Message-Data-High Register With DBO = 0 (CANMDH)..................................................................................894

Figure 14-41. Message-Data-Low Register With DBO = 1 (CANMDL)................................................................................... 894

Figure 14-42. Message-Data-High Register With DBO = 1 (CANMDH)..................................................................................894

Figure 15-1. SCI Block Diagram.............................................................................................................................................. 899

Figure 15-2. SCI/LIN Block Diagram....................................................................................................................................... 900

Figure 15-3. Typical SCI Data Frame Formats........................................................................................................................ 901

Figure 15-4. Asynchronous Communication Bit Timing...........................................................................................................902

Figure 15-5. Idle-Line Multiprocessor Communication Format................................................................................................904

Figure 15-6. Address-Bit Multiprocessor Communication Format........................................................................................... 905

Figure 15-7. Receive Buffers................................................................................................................................................... 906

Figure 15-8. Transmit Buffers.................................................................................................................................................. 906

Figure 15-9. General Interrupt Scheme................................................................................................................................... 907

Figure 15-10. Interrupt Generation for Given Flags.................................................................................................................908

Figure 15-11. LIN Protocol Message Frame Format: Master Header and Slave Response....................................................915

Figure 15-12. Header 3 Fields: Sync Break, Sync, and ID...................................................................................................... 915

Figure 15-13. Response Format of LIN Message Frame........................................................................................................ 916

Figure 15-14. Message Header in Terms of T

bit

..................................................................................................................... 918

Figure 15-15. ID Field.............................................................................................................................................................. 919

Figure 15-16. Measurements for Synchronization...................................................................................................................921

Figure 15-17. Synchronization Validation Process and Baud Rate Adjustment...................................................................... 922

Figure 15-18. Optional Embedded Checksum in Response for Extended Frames................................................................. 923

Figure 15-19. Checksum Compare and Send for Extended Frames.......................................................................................924

Figure 15-20. TXRX Error Detector......................................................................................................................................... 926

Figure 15-21. Classic Checksum Generation at Transmitting Node........................................................................................927

Figure 15-22. LIN 2.0-Compliant Checksum Generation at Transmitting Node...................................................................... 927

Figure 15-23. ID Reception, Filtering and Validation............................................................................................................... 928

Figure 15-24. LIN Message Frame Showing LIN Interrupt Timing and Sequence.................................................................. 931

Figure 15-25. Wakeup Signal Generation................................................................................................................................935

Figure 15-26. SCIGCR0 Register............................................................................................................................................ 941

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TMS320F2803x Microcontrollers 19

Figure 15-27. SCIGCR1 Register............................................................................................................................................ 942

Figure 15-28. SCIGCR2 Register............................................................................................................................................ 947

Figure 15-29. SCISETINT Register......................................................................................................................................... 949

Figure 15-30. SCICLEARINT Register.................................................................................................................................... 952

Figure 15-31. SCISETINTLVL Register................................................................................................................................... 955

Figure 15-32. SCICLEARINTLVL Register.............................................................................................................................. 958

Figure 15-33. SCIFLR Register............................................................................................................................................... 961

Figure 15-34. SCIINTVECT0 Register.....................................................................................................................................969

Figure 15-35. SCIINTVECT1 Register.....................................................................................................................................970

Figure 15-36. SCIFORMAT Register....................................................................................................................................... 970

Figure 15-37. BRSR Register.................................................................................................................................................. 972

Figure 15-38. SCIED Register................................................................................................................................................. 973

Figure 15-39. SCIRD Register.................................................................................................................................................973

Figure 15-40. SCITD Register................................................................................................................................................. 974

Figure 15-41. SCIPIO2 Register..............................................................................................................................................975

Figure 15-42. LINCOMP Register............................................................................................................................................976

Figure 15-43. LINRD0 Register............................................................................................................................................... 977

Figure 15-44. LINRD1 Register............................................................................................................................................... 978

Figure 15-45. LINMASK Register............................................................................................................................................ 979

Figure 15-46. LINID Register...................................................................................................................................................980

Figure 15-47. LINTD0 Register................................................................................................................................................981

Figure 15-48. LINTD1 Register................................................................................................................................................982

Figure 15-49. MBRSR Register............................................................................................................................................... 983

Figure 15-50. IODFTCTRL Register........................................................................................................................................984

List of Tables

Table 1-1. Flash/OTP Configuration Registers.......................................................................................................................... 38

Table 1-2. Flash Options Register (FOPT) Field Descriptions...................................................................................................39

Table 1-3. Flash Power Register (FPWR) Field Descriptions.................................................................................................... 39

Table 1-4. Flash Status Register (FSTATUS) Field Descriptions...............................................................................................40

Table 1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions.............................................................................41

Table 1-6. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions............................................... 41

Table 1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions................................................................................... 42

Table 1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions....................................................................................... 43

Table 1-9. Security Levels..........................................................................................................................................................44

Table 1-10. Resources Affected by the CSM.............................................................................................................................47

Table 1-11. Resources Not Affected by the CSM.......................................................................................................................47

Table 1-12. Code Security Module (CSM) Registers................................................................................................................. 53

Table 1-13. CSM Status and Control Register (CSMSCR) Field Descriptions.......................................................................... 53

Table 1-14. PLL, Clocking, Watchdog, and Low-Power Mode Registers...................................................................................54

Table 1-15. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions...................................................................... 55

Table 1-16. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions...................................................................... 57

Table 1-17. Peripheral Clock Control 2 Register (PCLKCR2) Field Descriptions...................................................................... 58

Table 1-18. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions...................................................................... 59

Table 1-19. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions.................................................... 60

Table 1-20. Internal Oscillator n Trim (INTOSCnTRIM) Register Field Descriptions................................................................. 62

Table 1-21. Clocking (XCLK) Field Descriptions........................................................................................................................63

Table 1-22. Clock Control (CLKCTL) Register Field Descriptions............................................................................................. 64

Table 1-23. Possible PLL Configuration Modes.........................................................................................................................67

Table 1-24. PLL Settings............................................................................................................................................................69

Table 1-25. PLL Status (PLLSTS) Register Field Descriptions..................................................................................................70

Table 1-26. PLL Lock Period (PLLLOCKPRD) Register Field Descriptions.............................................................................. 72

Table 1-27. NMI Interrupt Registers...........................................................................................................................................77

Table 1-28. NMI Configuration (NMICFG) Register Bit Definitions (EALLOW)..........................................................................77

Table 1-29. NMI Flag (NMIFLG) Register Bit Definitions (EALLOW Protected)........................................................................ 78

Table 1-30. NMI Flag Clear (NMIFLGCLR) Register Bit Definitions (EALLOW Protected)....................................................... 78

Table 1-31. NMI Flag Force (NMIFLGFRC) Register Bit Definitions (EALLOW Protected).......................................................79

Table 1-32. NMI Watchdog Counter (NMIWDCNT) Register Bit Definitions..............................................................................79

Table 1-33. NMI Watchdog Period (NMIWDPRD) Register Bit Definitions (EALLOW Protected)............................................. 80

Table 1-34. Low-Power Mode Summary....................................................................................................................................81

Table 1-35. Low Power Modes.................................................................................................................................................. 82

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20 TMS320F2803x Microcontrollers SPRUI10A – DECEMBER 2018 – REVISED JUNE 2022

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