探索Intel CPUID指令：功能与应用指南

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Intel CPUID API（Application Programming Interface）是一种处理器识别指令集，由英特尔公司提供，用于获取关于处理器的各种信息。该文档主要关注于Intel处理器的CPUID指令，这是一个低级且直接与硬件交互的指令，允许软件开发者获取关于处理器型号、功能特性和其他技术规格的重要数据。通过CPUID，程序可以查询以下信息： 1. **处理器型号和步进**：通过CPUID可以确定处理器的具体型号（如Core i7或Xeon）、系列号以及制造工艺的步进，这对于硬件识别和优化至关重要。 2. **微架构和特性支持**：了解处理器是否支持特定的指令集扩展（如SSE、AVX、FMA等），这对于依赖这些特性的软件性能至关重要。 3. **缓存大小和类型**：获取L1、L2和L3缓存的信息，这对于内存访问速度和系统整体性能有着直接影响。 4. **多媒体和安全特性**：查询处理器对多媒体指令的支持（如AES-NI、AVX-512）以及安全相关的功能（如TPM或SGX）。 5. **其他元数据**：比如制造日期、修订版本、特征标志（如是否支持超线程、虚拟化等）。然而，使用CPUID时需要注意的是，它并非所有处理器都支持，且存在一定的局限性。某些标记为“预留”或“未定义”的指令或字段可能是未来版本的预留，不应在当前设计中依赖。此外，文档还强调了Intel对销售和使用其产品的责任声明，即不承担任何有关特定用途适用性、商业可用性或侵犯知识产权的责任，并可能随时更改产品规格和描述。因此，在编写依赖CPUID的程序时，开发人员必须确保遵循最新的CPUID规范，并理解可能存在不稳定性和未来兼容性问题。同时，由于CPUID指令主要用于诊断和调试目的，不适合在医疗、生命维持等关键应用中使用，因为这些应用需要高度稳定和可靠的处理能力。

AP-485

Table 4. Intel486™, and Subsequent Processor Signatures

Extended

Family

Extended

Model

Type Family

Code

Model

Number

Stepping

Description

00000000 0000 00 0100 000x xxxx

(1)

Intel486™ DX processors

00000000 0000 00 0100 0010 xxxx

(1)

Intel486 SX processors

00000000 0000 00 0100 0011 xxxx

(1)

Intel487™ processors

00000000 0000 00 0100 0011 xxxx

(1)

IntelDX2™ processors

00000000 0000 00 0100 0011 xxxx

(1)

IntelDX2 OverDrive

processors

00000000 0000 00 0100 0100 xxxx

(3)

Intel486 SL processor

00000000 0000 00 0100 0101 xxxx

(1)

IntelSX2™ processors

00000000 0000 00 0100 0111 xxxx

(3)

Write-Back Enhanced IntelDX2 processors

00000000 0000 00 0100 1000 xxxx

(3)

IntelDX4™ processors

00000000 0000 0x 0100 1000 xxxx

(3)

IntelDX4 OverDrive processors

00000000 0000 00 0101 0001 xxxx

(2)

Pentium

processors (60, 66)

00000000 0000 00 0101 0010 xxxx

(2)

Pentium processors (75, 90, 100, 120, 133,

150, 166, 200)

00000000 0000 01

(4)

0101 0001 xxxx

(2)

Pentium OverDrive processor for Pentium

processor (60, 66)

00000000 0000 01

(4)

0101 0010 xxxx

(2)

Pentium OverDrive processor for Pentium

processor (75, 90, 100, 120, 133)

00000000 0000 01 0101 0011 xxxx

(2)

Pentium OverDrive processors for Intel486

processor-based systems

00000000 0000 00 0101 0100 xxxx

(2)

Pentium processor with MMX™ technology

(166, 200)

00000000 0000 01 0101 0100 xxxx

(2)

Pentium OverDrive processor with MMX™

technology for Pentium processor (75, 90,

100, 120, 133)

00000000 0000 00 0110 0001 xxxx

(2)

Pentium Pro processor

00000000 0000 00 0110 0011 xxxx

(2)

Pentium II processor, model 3

00000000 0000 00 0110 0101

(5)

xxxx

(2)

Pentium II processor, model 5, Pentium II

Xeon processor, model 5, and Intel

Celeron processor, model 5

00000000 0000 00 0110 0110 xxxx

(2)

Intel Celeron processor, model 6

00000000 0000 00 0110 0111

(6)

xxxx

(2)

Pentium III processor, model 7, and

Pentium III Xeon processor, model 7

00000000 0000 00 0110 1000

(7)

xxxx

(2)

Pentium III processor, model 8, Pentium III

Xeon processor, model 8, and Intel

Celeron processor, model 8

00000000 0000 00 0110 1010 xxxx

(2)

Pentium III Xeon processor, model A

00000000 0000 00 0110 1011 xxxx

(2)

Pentium III processor, model B

00000000 0000 01 0110 0011 xxxx

(2)

Intel Pentium II OverDrive processor

00000000 0000 00 1111 000x xxxx

(2)

Intel Pentium 4 processor or Intel Xeon

processor

AP-485

NOTES:

This processor does not implement the CPUID instruction.

Refer to the Intel486™ documentation, the Pentium® Processor Specification Update (Order Number 242480),

the Pentium® Pro Processor Specification Update (Order Number 242689), the Pentium® II Processor

Specification Update (Order Number 243337), the Pentium® II Xeon Processor Specification Update (Order

Number 243776), the Intel Celeron Processor Specification Update (Order Number 243748), the Pentium ® III

Processor Specification Update (Order Number 244453), the Pentium® III Xeon™ Processor Specification

Update (Order Number 244460), the Pentium® 4 Processor Specification Update (Order Number 249199) or the

Intel® Xeon™ Processor Specification Update (Order Number 249678) for the latest list of stepping numbers.

Stepping 3 implements the CPUID instruction.

The definition of the type field for the OverDrive® processor is 01h. An erratum on the Pentium OverDrive

processor will always return 00h as the type.

To differentiate between the Pentium II processor, model 5, Pentium II Xeon processor and the Intel Celeron

processor, model 5, software should check the cache descriptor values through executing CPUID instruction with

EAX = 2. If no L2 cache is returned, the processor is identified as an Intel Celeron processor, model 5. If 1M or

2M L2 cache size is reported, the processor is the Pentium II Xeon processor otherwise it is a Pentium II

processor, model 5 or a Pentium II Xeon processor with 512K L2 cache size.

To differentiate between the Pentium III processor, model 7 and the Pentium III Xeon processor, model 7,

software should check the cache descriptor values through executing CPUID instruction with EAX = 2. If 1M or

2M L2 cache size is reported, the processor is the Pentium III Xeon processor otherwise it is a Pentium III

processor or a Pentium III Xeon processor with 512K L2 cache size.

To differentiate between the Pentium III processor, model 8 and the Pentium III Xeon processor, model 8,

software should check the Brand ID values through executing CPUID instruction with EAX = 1.

AP-485

3.3 Feature Flags

When the EAX register contains a value of 1, the CPUID instruction (in addition to loading the processor signature

in the EAX register) loads the EDX and ECX register with the feature flags. The feature flags (when a Flag = 1)

indicate what features the processor supports. Table 5 lists the currently defined feature flag values.

For future processors, refer to the programmer’s reference manual, user’s manual, or the appropriate documentation

for the latest feature flag values.

Use the feature flags in your applications to determine which processor features are supported. By using the

CPUID feature flags to determine processor features, your software can detect and avoid incompatibilities

introduced by the addition or removal of processor features.

Table 5. Feature Flag Values Reported in the EDX Register

Bit

Name

Description when

Flag = 1

Comments

0 FPU

Floating-point unit on-

Chip

The processor contains an FPU that supports the Intel387

floating-point instruction set.

1 VME Virtual Mode Extension The processor supports extensions to virtual-8086 mode.

2 DE Debugging Extension

The processor supports I/O breakpoints, including the

CR4.DE bit for enabling debug extensions and optional

trapping of access to the DR4 and DR5 registers.

3 PSE Page Size Extension The processor supports 4-Mbyte pages.

4 TSC Time Stamp Counter

The RDTSC instruction is supported including the

CR4.TSD bit for access/privilege control.

5 MSR Model Specific Registers

Model Specific Registers are implemented with the

RDMSR, WRMSR instructions

6 PAE

Physical Address

Extension

Physical addresses greater than 32 bits are supported.

7 MCE

Machine Check

Exception

Machine Check Exception, Exception 18, and the

CR4.MCE enable bit are supported

8 CX8

CMPXCHG8 Instruction

Supported

The compare and exchange 8 bytes instruction is

supported.

9 APIC

On-chip APIC Hardware

Supported

The processor contains a software-accessible Local APIC.

10 Reserved Do not count on their value.

11 SEP Fast System Call

Indicates whether the processor supports the Fast System

Call instructions, SYSENTER and SYSEXIT. NOTE: Refer

to Section 3.4 for further information regarding

SYSENTER/ SYSEXIT feature and SEP feature bit.

12 MTRR

Memory Type Range

Registers

The Processor supports the Memory Type Range

Registers specifically the MTRR_CAP register.

13 PGE Page Global Enable

The global bit in the page directory entries (PDEs) and

page table entries (PTEs) is supported, indicating TLB

entries that are common to different processes and need

not be flushed. The CR4.PGE bit controls this feature.

14 MCA

Machine Check

Architecture

The Machine Check Architecture is supported, specifically

the MCG_CAP register.

15 CMOV

Conditional Move

Instruction Supported

The processor supports CMOVcc, and if the FPU feature

flag (bit 0) is also set, supports the FCMOVCC and FCOMI

instructions.

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