"TMDS171 HDMI接收器技术文档: HDMI重定时器和接口单元详解"

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The TI-TMDS171.pdf document provides detailed information about the TMDS171 HDMI Receiver, which is used for HDMI/DVI connectivity in digital TVs and other audiovisual processing units. The document outlines the pin configurations for the IN_CLKp/n, OUT_CLKp/n, IN_D1p/n, OUT_D1p/n, IN_D0p/n, OUT_D0p/n, OUT_D2p/n, and IN_D2p/n connections, as well as the 3.3V to 5V power requirements. It also specifies the SDA_SRC, SCL_SRC, SDA_SNK, SCL_SNK, HPD_SRC, HPD_SNK, SDA_CTL, and SCL_CTL pins, as well as the TMDS RXD, DCHPD, I2C, and EVSADJ connections. In addition to the pin configurations, the document provides information on the HDMI SW/HD unit, the audiovisual processing unit, and the interface unit. It also outlines the copyright information for the Texas Instruments Incorporated product, as well as details on where to access the product folder, order information, technical documents, and tools. Overall, the TI-TMDS171.pdf document serves as a comprehensive guide for understanding and implementing the TMDS171 HDMI Receiver in digital TV and audiovisual processing applications. It provides detailed technical information and specifications, making it a valuable resource for engineers and developers working with HDMI/DVI connectivity.

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

Switching Characteristics (continued)

The Maximum rating is simulated at 3.465 V V

and 1.27 V V

and at 85°C temperature. The Typical rating is simulated at

3.3 V V

and 1.2 V V

and at 27°C temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) The Maximum rating is simulated at 3.465 V V

and 1.27 V V

(2) Cb = total capacitance of one bus line in pF.

SK_INTRA

Intra-pair output skew

Default setting for internal intra-pair

skew adjust, PRE_SEL = NC;

TX_TERM_CTL = NC, DR ≤ 3.4

Gbps; See Figure 6

0.15 Tbit

JITC2

Total output clock jitter CLK Rate ≤ 340 MHz 0.25 Tbit

JITD2

Total output data jitter DR ≤ 3.4 Gbps; See Figure 11 0.2 Tbit

HPD

PD(HPD)

Propagation delay from HPD_SNK

to HPD_SRC; rising edge and falling

edge

(1)

see Figure 13; not valid during

switching time

40 120 ns

T(HPD)

HPD logical disconnected timeout see Figure 14 2 ms

DDC and I2C

Rise time of both SDA and SCL

signals

= 3.3 V 300

Fall time of both SDA and SCL

signals

300

HIGH

Pulse duration, SCL high 0.6

µs

LOW

Pulse duration, SCL low 1.3

SU1

Setup time, SDA to SCL 100 ns

ST,STA

Setup time, SCL to start condition 0.6

µs

HD,STA

Hold time, start condition to SCL 0.6

ST,STO

Setup time, SCL to stop condition 0.6

(BUF)

Bus free time between stop and start

condition

1.3

PLH1

Propagation delay time, low-to-high-

level output

Source to Sink:100 kbps pattern;

b(Sink)

= 400 pF

(2)

; see Figure 17

360

PHL1

Propagation delay time, high-to-low-

level output

230

PLH2

Propagation delay time, low-to-high-

level output

Sink to Source: 100 kbps pattern;

b(Source)

= 100 pF

(2)

; see Figure 18

250

PHL2

Propagation delay time, high-to-low-

level output

200

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