Keysight C7515B ENDC 测试总结与配置指南

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"Keysight C7515B ENDC测试总结" 本文档详细介绍了使用Keysight C7515B进行EN-DC(增强型移动宽带)测试的过程和步骤,主要关注环境配置、小区设置和激活等方面。EN-DC是5G NSA(非独立组网)模式的一种,它结合了4G LTE网络和5G NR网络,以提供更高效的数据传输和无缝连接。 1. 环境配置与注册 在开始测试之前,需要正确配置测试环境。这包括选择合适的场景(Scenario),比如"NR_2DL4*4_2UL2*2_LTE_1CC",这是一个包含一个LTE载波和两个NR小区的场景,支持NSA和SA(独立组网)模式。在切换场景时,需确保TestApp处于关闭状态。在UXM上,配置了两个NR小区,每个支持下行4天线传输(4x4 MIMO)和上行2天线传输(2x2 MIMO)。 2. 小区配置与激活 使用5G NR Test App进行小区配置。打开App可能需要一段时间,之后可以导入预先调试好的SCPI(System Control Programming Interface)脚本,这些脚本包含了NR小区的配置信息。值得注意的是,SCPI脚本通常不会覆盖LTE小区的配置,因此LTE小区需要手动设置。 - 导入SCPI脚本:通过Utility菜单选择Export/Import SCPI -> Import,然后选择所需的脚本文件。加载完成后,可能会出现警告,但不影响脚本的正常运行。 3. 激活LTE小区 在配置界面,选择需要激活的LTE小区。LTE小区的参数需要单独设定,这包括频段、带宽、TAC(跟踪区域码)以及其他必要参数。激活小区后,设备应能成功注册到网络。 4. 测试流程 完成小区配置和激活后,设备将进行EN-DC的注册过程。这包括手机开机并尝试连接到4G和5G网络。在EN-DC模式下,手机会同时连接到LTE和NR小区,实现数据的高效传输。 总结: Keysight C7515B是进行EN-DC测试的关键工具,它提供了对5G NR和4G LTE小区的全面配置和管理功能。通过精心设置场景、导入SCPI脚本以及激活小区,可以确保测试环境符合EN-DC的要求,从而进行有效的网络性能验证和问题排查。测试过程中需要注意每个步骤的细节,确保所有配置正确无误,以获取准确的测试结果。

改写一下这段代码,使得寄存器地址支持16bit读写,现在这段是只支持8bit读写://FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase

2023-06-09 上传

always @(posedge clk or negedge rst_n) if(!rst_n) begin key_v <= 4'b0000; new_value <= 4'd0; new_rdy <= 1'b0; end else begin case(cstate) K_IDLE: begin key_v <= 4'b0000; new_value <= 4'd0; new_rdy <= 1'b0; end K_H1OL: begin key_v <= 4'b1110; new_value <= 4'd0; new_rdy <= 1'b0; end K_H2OL: begin case(key_h) 4'b1110: begin key_v <= 4'b0000; new_value <= 4'd0; new_rdy <= 1'b1; end 4'b1101: begin key_v <= 4'b0000; new_value <= 4'd1; new_rdy <= 1'b1; end 4'b1011: begin key_v <= 4'b0000; new_value <= 4'd2; new_rdy <= 1'b1; end 4'b0111: begin key_v <= 4'b0000; new_value <= 4'd3; new_rdy <= 1'b1; end default: begin key_v <= 4'b1101; new_value <= 4'd0; new_rdy <= 1'b0; end endcase end K_H3OL: begin case(key_h) 4'b1110: begin key_v <= 4'b0000; new_value <= 4'd4; new_rdy <= 1'b1; end 4'b1101: begin key_v <= 4'b0000; new_value <= 4'd5; new_rdy <= 1'b1; end 4'b1011: begin key_v <= 4'b0000; new_value <= 4'd6; new_rdy <= 1'b1; end 4'b0111: begin key_v <= 4'b0000; new_value <= 4'd7; new_rdy <= 1'b1; end default: begin key_v <= 4'b1011; new_value <= 4'd0; new_rdy <= 1'b0; end endcase end K_H4OL: begin case(key_h) 4'b1110: begin key_v <= 4'b0000; new_value <= 4'd8; new_rdy <= 1'b1; end 4'b1101: begin key_v <= 4'b0000; new_value <= 4'd9; new_rdy <= 1'b1; end 4'b1011: begin key_v <= 4'b0000; new_value <= 4'd10; new_rdy <= 1'b1; end 4'b0111: begin key_v <= 4'b0000; new_value <= 4'd15; new_rdy <= 1'b1; end default: begin key_v <= 4'b0000; new_value <= 4'd0; new_rdy <= 1'b0; end endcase end default: ; endcase end

2023-06-12 上传