改写一下这段代码，使得寄存器地址支持16bit读写，现在这段是只支持8bit读写：//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase

//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=4'b0000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 4'b0000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 4'b0001;//start else next_i2c_state <= i2c_state; end 4'b0001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=4'b0000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=4'b0010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=4'b0011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=4 'b0000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 4'b0010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=4'b0000; else if (startf)next_i2c_state<=4'b0001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=4'b0010 else next i2c_state<=i2c_state; end 4'b0011: //This state is the register data read begin if (stopf)next_i2c _state<=4'b0000; else if (startf) next_i2c _state<=4'b0001; else next_12c_state<=i2c_state; end 4'b0100: //This state is the register data write begin if (stopf)next_i2c _state<=4'b0000; else if (startf) next_i2c _state<=4b'0001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 4'b0000; endcase

修改后的代码中，将状态机的状态从原来的3位改为4位，扩展了状态数，以支持16bit的读写操作。在判断设备地址时，判断了设备地址的高8位和低8位，以支持16bit地址的读写操作。在读写寄存器数据时，保持原有的操作不变，不做改动。