改写一下这段代码，使得寄存器地址支持16bit读写，现在这段是只支持8bit读写，需要再添加一个状态机状态，使得寄存器高八位地址检测后有一个ack响应位，而不是直接改变寄存器地址的位宽：：//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase

//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=4'b0000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 4'b0000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 4'b0010;//start else next_i2c_state <= i2c_state; end 4'b0010://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=4'b0000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[15:1])) begin //write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 next_i2c_state<=4'b0100; ack <= 1'b1; end else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[15:1])) begin //read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 next_i2c_state<=4'b0110; ack <= 1'b1; end else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c_state<=4'b0000;//when the address accepted does not match the SADR, //the state comes back else begin next_i2c_state<=4'b0010; ack <= 1'b0; end end 4'b0100: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=4'b0000; else if (startf)next_i2c_state<=4'b0010; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c_state<=4'b1000; else next_i2c_state<=4'b0100; end 4'b0110: //This state is the register data read begin if (stopf)next_i2c_state<=4'b0000; else if (startf) next_i2c_state<=4'b0010; else next_i2c_state<=4'b0110; end 4'b1000: //This state is the register data write begin if (stopf)next_i2c_state<=4'b0000; else if (startf) next_i2c_state<=4'b0010; else next_i2c_state<=4'b1000; end default://safe mode control next_i2c_state <= 4'b0000; endcase

注释：在原有代码的基础上，添加了一个状态机状态，即4'b0010，用于检测高8位地址，并在地址检测后发送一个ack响应位。同时，将寄存器地址的位宽改为16位。