JESD230B标准：3D NAND Flash测试指南
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"JESD230B是JEDEC固态技术协会发布的关于NAND Flash接口互操作性的标准，该标准详细定义了3D Flash、MLC、TLC和SLC等不同类型的闪存测试方法。这个标准更新自JESD2320A，旨在确保在不违反版权法律的情况下，促进制造商与购买者之间的理解和合作，提高产品的可互换性和性能，并帮助购买者快速准确地选择适用的产品。"
JESD230B标准是针对NAND闪存设备测试的重要参考，它涵盖了各种闪存技术的最新测试规范。3D Flash是指三维堆叠的闪存技术，这种技术通过垂直堆叠多个存储单元来提高存储密度和性能。MLC（Multi-Level Cell）是一种多层单元技术，每个存储单元可以存储2位数据；TLC（Triple-Level Cell）进一步扩展，每个单元存储3位；而SLC（Single-Level Cell）是最基础的单元，每个单元仅存储1位数据。这些不同的技术各有优缺点，例如SLC速度快、寿命长但成本较高，而TLC则具有更高的存储密度但可能牺牲一些速度和耐用性。
在JESD230B中，测试方法包括但不限于以下几个方面：
1. **读写速度测试**：评估闪存设备的读取和写入速率，这是衡量其性能的关键指标。
2. **耐用性测试**：检查闪存的擦写次数（P/E周期），确保其达到制造商承诺的使用寿命。
3. **错误纠正能力测试**：验证ECC（Error Correction Code）算法在面对数据错误时的修复能力。
4. **可靠性测试**：包括高温工作、低温工作、湿度等环境条件下的稳定性测试。
5. **兼容性测试**：确保设备与各种控制器和主机接口的互操作性。
6. **功耗测试**：评估设备在不同工作状态下的能耗。
7. **数据保持时间测试**：确定未供电状态下，闪存能够保留数据的时间。
标准的制定是为了消除制造商和消费者之间的误解，通过标准化流程确保产品的一致性和质量。此外，JEDC的标准和出版物经过了其董事会、法律顾问的审查，旨在服务于全球公众利益，促进产品的改进和快速获取。
遵循JESD230B标准进行测试，可以帮助制造商确保其NAND Flash产品满足行业要求，同时也能帮助消费者和企业选择符合需求、性能稳定且可靠的闪存解决方案。对于研发、制造、销售和使用闪存设备的公司来说，理解并应用这个标准至关重要。
JEDEC Standard No. 230B
Page 5
2.6 Pin description
Table 1 — Pin description
Name
Input/
Output
Description
IO0 ~ IO7(~ IO15)
DQ0 ~ DQ7
DQ0_x ~ DQ7_x
I/O
DATA INPUTS/OUTPUTS
These signals are used to input command, address and data, and to output data
during read operations. The signals float to high-z when the chip is deselected or
when the outputs are disabled. IO0 ~ IO15 are used in a 16-bit wide target
configuration. With multi channel support, IO0_0~IO7_0 and IO0_1~IO7_1 are
used for IOs of channel 0 and IOs of channel 1 respectively. Also known as
DQ0~DQ7 for Toggle DDR and Synchronous DDR.
The number after the underscore represents the channel. For example, DQ0_0
indicates DQ0 of channel-0 and DQ0_1 does DQ0 of channel-1.
CLE_x I
COMMAND LATCH ENABLE
The CLE_x signal is one of the signals used by the host to indicate the type of
bus cycle (command, address, data).
ALE_x I
ADDRESS LATCH ENABLE
The ALE_x signal is one of the signals used by the host to indicate the type of
bus cycle (command, address, data).
CEx_x_n I
CHIP ENABLE
The CEx_x_n input is the target selection control. When CEx_x_n is high and
the target is in the ready state, the target goes into a low-power standby state.
When CEx_x_n is low, the target is selected.
The number after the first underscore represents the channel. For example,
CE0_0_n indicates CE0_n of channel-0 and CE0_1_n does CE0_n of channel-
1.
WE_x_n I
WRITE ENABLE
The WE_x_n input controls writes to the I/O port. For Asynchronous SDR Data,
commands, addresses are latched on the rising edge of the WE_x_n pulse. For
Toggle DDR commands, addresses are latched on the rising edge of the
WE_x_n pulse.
R/B_x_n O
READY/BUSY OUTPUT
The R/B_x_n output indicates the status of the target operation. When low, it
indicates that one or more operations are in progress and returns to high state
upon completion. It is an open drain output and does not float to high-z condition
when the chip is deselected or when outputs are disabled.
RE_x_n
(RE_x_t)
I
READ ENABLE
The RE_x_n input is the serial data-out control. For Asynchronous SDR Data is
valid tREA after the falling edge and for Toggle DDR Data is valid after the falling
edge & rising edge of RE_x_n which also increments the internal column
address counter by each one.
RE_x_c I
Complement of Read Enable
This is the complementary signal to Read Enable
DQS_x
(DQS_x_t)
I/O
Data Strobe
The data strobe signal that indicates the data valid window for Toggle DDR and
Synchronous DDR data interface. Output with read data, input with write data.
Edge-aligned with read data, centered in write data.
DQS_x_c I/O
Complement of Data Strobe
This is the complementary signal to Data Strobe.
W/R_x I
Write/Read Direction
The Write/Read Direction signal indicates the owner of the DQ bus and DQS
signal in the Synchronous DDR data interface. This signal shares the same pin
as RE_x_n in the asynchronous data interface.
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