TI DS90UB953-Q1中文规格书：汽车应用FPD-LinkIII串行器

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"DS90UB953-Q1是TI公司的一款高性能串行器，专为汽车领域的应用设计，适用于2.3MP/60fps摄像头、雷达和其他传感器，支持MIPI CSI-2接口的FPD-LinkIII 4.16Gbps串行传输。" 这篇文档主要介绍了DS90UB953-Q1的关键特性及其在汽车电子系统中的应用。该器件满足AEC-Q100标准，确保了在-40°C至+105°C的汽车工作环境下稳定运行，并符合ISO10605和IEC61000-4-2 ESD标准，保证了设备的抗静电能力。此外，它还是一款同轴电缆供电（PoC）兼容的收发器，简化了电源配置。 DS90UB953-Q1支持高速传感器，如全高清1080p2MP60fps和4MP30fps的图像传感器，其数据速率可达4.16Gbps。与D-PHY v1.2和CSI-2 v1.3标准兼容，可以实现多达4个数据通道，每个通道速度高达832Mbps，且能处理最多4个虚拟通道，增强了系统的灵活性和扩展性。在同步和时钟管理方面，DS90UB953-Q1提供精确的多传感器时钟和同步功能，确保多个传感器间的数据一致性。它还配备了一个灵活的可编程输出时钟发生器，适应不同的系统需求。为了保证数据的完整性和安全性，该器件包含了CRC数据保护、传感器数据完整性检查、I2C写保护等高级数据保护机制，同时具备电压和温度测量、可编程警报器以及线路故障检测功能，增强了系统的诊断和故障预防能力。此外，DS90UB953-Q1与DS90UB954-Q1或DS90UB960-Q1解串行器配合使用，构成完整的串行传输解决方案，能够在长距离传输中保持高数据质量和稳定性。该器件的I2C接口和高速GPIO（HS-GPIO）进一步增强了其在复杂系统集成中的交互性和控制能力。总结来说，DS90UB953-Q1是汽车电子系统中连接高速图像传感器到处理单元的理想选择，具备高效能、高可靠性以及多种保护和诊断特性，适应了现代汽车对图像处理和传感器数据传输的严格要求。

DOUT+

DPHY

Receiver

FIFO

Encoder/

Formatter

Serializer

Cable

Driver

Clock Gen

BCC

Receiver

Controller

I2C

Controller

FIFO

Decode/

Encode

Clock/Data

Recovery

CLK_OUT

CLKIN

MODE

/ IDX

I2C_SDA

I2C_SCL

CSI-2

PDB

bias_internal

DOUT-

Internal AON Clock

DS90UB953-Q1

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7 Detailed Description

7.1 Overview

The DS90UB953-Q1 serializes data from high-resolution image sensors or other sensors using the MIPI CSI-2

interface. The DS90UB953-Q1 serializer is optimized to interface with the DS90UB954-Q1 deserializer (dual hub)

or the DS90UB960-Q1 deserializer (quad hub) as well as potential future deserializers. The interconnect between

the serializer and the deserializer can be either a coaxial cable or shielded-twisted pair (STP) cable. The

DS90UB953-Q1 was designed to support multi-sensor systems such as surround view, and as such has the

ability to synchronize sensors through the DS90UB954-Q1 and DS90UB960-Q1 hubs.

The DS90UB953-Q1 serializer and companion deserializer incorporate an I

C-compatible interface. The I

C-

compatible interface allows programming of serializer or deserializer devices from a local host controller. In

addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between the

serializer and deserializer as well as remote I

C slave devices.

The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I

C transactions across the serial link

from one I

C bus to another.

7.2 Functional Block Diagram

KEY:

ST ± Start of Transmission PH ± Packet Header

ET ± End of Transmission PF ± Packet Footer

LPS ± Low Power State

DATA:

DATA DATAPFPH PH PFSP SP

LPS

ET ST

LPS

ET STST

LPS

ET ST ET

Short

Packet

Long

Packet

Long

Packet

Short

Packet

DS90UB953-Q1

ZHCSGW1B –SEPTEMBER 2017 –REVISED SEPTEMBER 2018

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7.3 Feature Description

The DS90UB953-Q1 FPD-Link III serializer is designed to support high-speed raw data sensors including 2-MP

imagers at 60 fps as well as 4-MP, 30-fps cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors.

The chip features a forward channel capable of up to 4.16 Gbps and an ultra-low latency 50-Mbps bidirectional

control channel. The transmission of the forward channel, bidirectional control channel, and power is supported

over coaxial (Power-over-Coax) or STP cables. The DS90UB953-Q1 features advanced data protection and

diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the

DS90UB953-Q1 delivers precise multi-camera sensor clock and sensor synchronization.

7.3.1 CSI-2 Receiver

The DS90UB953-Q1 receives CSI-2 video data from the Sensor. During CSI-2 operation, the D-PHY consists of

a clock lane and one or more data lanes. The DS90UB953-Q1 is a Slave Device and only supports

Unidirectional Lane in the Forward direction. Low Power Escape mode is not supported.

7.3.1.1 CSI-2 Receiver Operating Modes

During normal operation a Data Lane will be in either Control or High-Speed mode. In High-Speed mode, the

data transmission happens in a burst and starts and ends at a Stop state (LP-11). There is a transition state to

take the D-PHY from a Normal mode to the Low-Power state.

The sequence to enter High-Speed mode is: LP-11, LP-01, LP-00. After the sequence is entered, the Data Lane

remains in High-Speed mode until a Stop state (LP-11) is received.

7.3.1.2 CSI-2 Receiver High-Speed Mode

During high-speed data transmission, the digital D-PHY will enable termination signal to allow proper termination

of the HS RX of the Analog D-PHY, and the LP RX should stay at LP-00 state. Both CSI-2 data lane and clock

lane operate in the same manner. The DS90UB953-Q1 supports CSI-2 continuous clock lane mode where the

clock lane remains in high-speed mode.

7.3.1.3 CSI-2 Protocol Layer

There are two different types of CSI-2 packets: a short packet and a long packet. Short packets have information

such as the Frame Start/ Line Start, and long packets carry the data after the frame start is asserted. 图 4 shows

the structure of the CSI-2 protocol layer with short and long packets. The DS90UB953-Q1 supports 1, 2, and 4

lane configurations.

图图 4. CSI-2 Protocol Layer With Short and Long Packets

7.3.1.4 CSI-2 Short Packet

The short packet provides frame or line synchronization. 图 5 shows the structure of a short packet. A short

packet is identified by data types 0x00 to 0x0F.

16-Bit

Word Count

ECC

Data ID

Data 0

Data 1

Data 2

Data 3

Data WC-4

Data WC-3

Data WC-2

Data WC-1

16-bit

Checksum

32-bit

PACKET

HEADER

(PH)

16-bit

PACKET

FOOTER

(PF)

PACKET DATA:

Length = Word Count (WC) * Data Word

Width (8-bits). There are NO restrictions

on the values of the data words

16-Bit

Short Packet

Data Field

VCX + ECC

Data ID

32-bit SHORT PACKET (SH)

Data Type (DT) = 0x00 ± 0x0F

DS90UB953-Q1

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ZHCSGW1B –SEPTEMBER 2017–REVISED SEPTEMBER 2018

Feature Description (接接下下页页)

图图 5. CSI-2 Short Packet Structure

7.3.1.5 CSI-2 Long Packet

A long packet consists of three elements: a 32-bit packet header (PH), an application-specific data payload with

a variable number of 8-bit data words, and a 16-bit packet footer (PF). The packet header is further composed of

three elements: an 8-bit data identifier, a 16-bit word count field, and an 8-bit ECC. The packet footer only has

one element—a 16-bit checksum. 图 6 shows the structure of a long packet.

图图 6. CSI-2 Long Packet Structure

表表 1. CSI-2 Long Packet Structure Description

PACKET

PART

FIELD NAME SIZE (BIT) DESCRIPTION

Header

VC / Data ID 8 Contains the virtual channel identifier and the data-type information.

Word Count 16 Number of data words in the packet data. A word is 8 bits.

ECC 8

ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit

error detection.

Data Data WC × 8 Application-specific payload (WC words of 8 bits).

Footer Checksum 16 16-bit cyclic redundancy check (CRC) for packet data.

7.3.1.6 CSI-2 Errors and Detection

7.3.1.6.1 CSI-2 ECC Detection and Correction

CSI-2 packet header contains 6-bit Error Correction Code (ECC). ECC code in the 32-bit long packet header can

be corrected when there is a 1-bit error and detected when there is a 2-bit error. This feature is added to monitor

the CSI-2 input for ECC 1-bit error correction. When ECC error is detected, ECC error detection register will be

set and an alarm indicator bit can be sent to the Deserializer to indicate the ECC error has been detected. A

DS90UB953-Q1

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7.3.1.6.2 CSI-2 Check Sum Detection

A CSI-2 long packet header contains a 16-bit check sum before the end of transmission. The DS90UB953-Q1

calculates the check sum of the incoming CSI-2 data. If a check sum error is detected, the check sum error

status will be saved in the CSI_ERR_STATUS register (0x5D) and can also be forwarded to the deserializer

through the bidirectional control channel.

7.3.1.6.3 D-PHY Error Detection

DS90UB953-Q1 detect and reports SoT and SoT Sync errors.

7.3.1.6.4 CSI-2 Receiver Status

For the Receive ports, several status functions can be tracked and monitored through register access. The status

indications are available for error conditions as well as indications of change in line length measurements. These

are available through the CSI_ERR_CNT (0x5C), CSI_ERR_STATUS (0x5D), CSI_ERR_DLANE01 (0x5E),

CSI_ERR_DLANE23 (0x5F), and CSI_ERR_CLK_LANE (0x60) registers.

7.3.2 FPD-Link III Forward Channel Transmitter

The DS90UB953-Q1 features a high-speed signal transmitter capable of driving signals at rates of up to 4.16

Gbps.

7.3.2.1 Frame Format

The DS90UB953-Q1 formats the data into 40-bit long frames. Each frame is encoded to ensure DC balance and

to ensure sufficient data line transitions. Each frame contains video payload data, I

C forward channel data, CRC

information, framing information, and information regarding the state of the CSI-2 interface.

7.3.3 FPD-Link III Back Channel Receiver

The FPD-Link III back channel receives an encoded back channel signal over the FPD-Link III interface. The

back channel frame is a 30-bit frame that contains I

C commands and GPIO data. The back channel frame

receives an encoded clock and data from the deserializer, thus the data bit rate is one-half the frequency of the

highest frequency received.

The back channel frequency is programmable for operation with compatible deserializers. The default setting is

determined by the MODE strap pin. For operation with the DS90UB954-Q1 or DS90UB960-Q1, the back channel

should be programmed for 50-Mbps operation in DS90UB953-Q1 Synchronous mode and programmed for 10-

Mbps operation for non-synchronous modes.

7.3.4 Serializer Status and Monitoring

The DS90UB953-Q1 features enhanced FPD-Link III diagnostics, system monitoring, and Built-In Self Test

capabilities. It monitors forward channel and back channel data for errors and reports them in the status

registers. It also supports voltage and temperature measurement for system level diagnostics. The Built-In Self

Test feature allows testing of the forward channel and back channel data transmissions without external data

connections.

7.3.4.1 Forward Channel Diagnostics

The DS90UB953-Q1 monitors the status of the forward channel link. The forward channel high-speed PLL lock

status is reported in the HS_PLL_LOCK bit (Register 0x52[2]). When paired with the DS90UB954-Q1, the FPD-

Link III deserializer LOCK status is also reported in the RX_LOCK_DETECT bit (Register 0x52[6]).

7.3.4.2 Back Channel Diagnostics

The DS90UB953-Q1 monitors the status of the back channel link. The back channel CRC errors are reported in

the CRC_ERR bit (Register 0x52[1]). The number of CRC errors are stored in the CRC error counters and

reported in the CRC_ERR_CNT1 (Register 0x55) and CRC_ERR_CNT2 (Register 0x56) registers. The CRC

error counters are reset by setting the CRC_ERR_CLR (Register 0x49[3]) to 1.

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