8
Philips Semiconductors
The I
2
C-bus specification
Generation of clock signals on the I
2
C-bus is always the
responsibility of master devices; each master generates its
own clock signals when transferring data on the bus. Bus
clock signals from a master can only be altered when they
are stretched by a slow-slave device holding-down the
clock line, or by another master when arbitration occurs.
5 GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a
positive supply voltage via a current-source or pull-up
resistor (see Fig.3). When the bus is free, both lines are
HIGH. The output stages of devices connected to the bus
must have an open-drain or open-collector to perform the
wired-AND function. Data on the I
2
C-bus can be
transferred at rates of up to 100 kbit/s in the
Standard-mode, up to 400 kbit/s in the Fast-mode, or up to
3.4 Mbit/s in the High-speed mode. The number of
interfaces connected to the bus is solely dependent on the
bus capacitance limit of 400 pF. For information on
High-speed mode master devices, see Section 13.
6 BIT TRANSFER
Due to the variety of different technology devices (CMOS,
NMOS, bipolar) which can be connected to the I
2
C-bus,
the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not
fixed and depend on the associated level of V
DD
(see
Section 15 for electrical specifications). One clock pulse is
generated for each data bit transferred.
6.1 Data validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW (see Fig.4).
Fig.3 Connection of Standard- and Fast-mode devices to the I
2
C-bus.
MBC631
SCLKN1
OUT
SCLK
IN
SCLK
DATAN1
OUT
DATA
IN
DEVICE 1
SDA (Serial Data Line)
SCL (Serial Clock Line)
SCLKN2
OUT
SCLK
IN
SCLK
DATAN2
OUT
DATA
IN
DEVICE 2
V
DD
R
p
R
p
pull-up
resistors
剩余45页未读，继续阅读
sloth1600
- 粉丝: 2
- 资源: 7
我的内容管理
展开
最新资源
- 十种常见电感线圈电感量计算公式详解
- 军用车辆：CAN总线的集成与优势
- CAN总线在汽车智能换档系统中的作用与实现
- CAN总线数据超载问题及解决策略
- 汽车车身系统CAN总线设计与应用
- SAP企业需求深度剖析：财务会计与供应链的关键流程与改进策略
- CAN总线在发动机电控系统中的通信设计实践
- Spring与iBATIS整合：快速开发与比较分析
- CAN总线驱动的整车管理系统硬件设计详解
- CAN总线通讯智能节点设计与实现
- DSP实现电动汽车CAN总线通讯技术
- CAN协议网关设计：自动位速率检测与互连
- Xcode免证书调试iPad程序开发指南
- 分布式数据库查询优化算法探讨
- Win7安装VC++6.0完全指南：解决兼容性与Office冲突
- MFC实现学生信息管理系统：登录与数据库操作
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
