STM32L011x系列：超低功耗MCU，媲美MSP430的数据手册

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STM32超低功耗芯片datasheet详细介绍了ARM架构的Cortex-M0+微控制器STM32L011x3和STM32L011x4的特点，特别针对那些对功耗敏感的应用设计。该芯片提供极低的功耗解决方案，适用于电池驱动或能源受限的设备。首先，这款MCU在供电方面表现出色，工作电压范围宽广，从1.65V到3.6V，兼容性强。在温度适应性上，它可以在-40℃至125℃的极端环境下稳定运行。在节能模式下，睡眠状态下仅需0.23μA，当唤醒两个引脚时；而进入停机模式（STOP模式）时，功耗进一步降低至0.29μA（16个唤醒线）或0.54μA（加上RTC和2KB RAM保持）。运行模式下的功耗控制也十分优秀，最低可达到76μA/MHz，表明其在高效处理任务时仍能保持极低的电流消耗。此外，唤醒时间只需5μs，从Flash内存启动速度迅速。在12位ADC转换性能上，即使在高采样率（10ksps）下，功耗也只有41μA。作为核心，STM32L011x3/4基于Cortex-M0+内核，最高时钟频率可达32MHz，具有0.95 DMIPS/MHz的性能。安全性和电源管理方面，芯片提供了超安全的低功耗棕色-out复位（BOR）功能，支持5个可选阈值，以及超低功耗的上电/掉电复位（POR/PDR）。内置电压检测器（PVD）确保系统在不同电源条件下的稳定性。时钟源丰富多样，包括外部时钟（0到32MHz）、用于RTC校准的32kHz振荡器、工厂预设的高精度16MHz内部RC振荡器（±1%），以及低功耗的多速内部振荡器，从65kHz到4.2MHz，甚至还有用于CPU时钟的PLL。值得注意的是，芯片还预装了支持USART和SPI的固件加载器，便于开发过程中的调试和升级。这款STM32L011x3/4微控制器凭借其卓越的低功耗特性、广泛的时钟选项和便捷的接口，为嵌入式应用设计者提供了理想的平台，特别是在追求能源效率和长时间待机的物联网(IoT)设备中。

Functional overview STM32L011x3/4

16/119 DocID027973 Rev 5

Table 3. Functionalities depending on the operating power supply range

Operating power supply range

Functionalities depending on the operating power

supply range

ADC operation

Dynamic voltage scaling

range

= 1.65 to 1.71 V

ADC only, conversion time

up to 570 ksps

Range 2 or

range 3

= 1.71 to 1.8 V

(1)

1. CPU frequency changes from initial to final must respect the condition: f

CPU initial

<4f

CPU initial

. It must also

respect 5 μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch

from 4.2 MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.

ADC only, conversion time

up to 1.14 Msps

Range 1, range 2 or range 3

= 1.8 to 2.0 V

(1)

Conversion time up to 1.14

Msps

Range1, range 2 or range 3

= 2.0 to 2.4 V

Conversion time up to 1.14

Msps

Range 1, range 2 or range 3

= 2.4 to 3.6 V

Conversion time up to 1.14

Msps

Range 1, range 2 or range 3

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 2

32 kHz to 4.2 MHz (0ws) Range 3

Functional overview STM32L011x3/4

18/119 DocID027973 Rev 5

3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication

between peripherals, thus saving CPU resources and power consumption. In addition,

these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power

run, Low-power sleep and Stop modes.

Comparators O O O O O O - -

16-bit timers O O O O - - - -

LPTIM O O O O O O - -

IWDG O O O O O O O O

WWDG O O O O - - - -

SysTick Timer O O O O - - - -

GPIOs O O O O O O - 2 pins

Wakeup time to

Run mode

0 µs 6 CPU cycles 3 µs

7 CPU

cycles

5µs 65µs

Consumption

=1.8 to 3.6 V

(Typ)

Down to

128 µA/MHz

(from Flash)

Down to

31 µA/MHz

(from Flash)

Down to

7µA

Down to

3.8 µA

0.29 µA (No

RTC) V

=1.8 V

0.18 µA (No

RTC) V

=1.8 V

0.54 µA (with

RTC) V

=1.8 V

0.41 µA (with

RTC) V

=1.8 V

0.34 µA (No

RTC) V

=3.0 V

0.23 µA (No

RTC) V

=3.0 V

0.67 µA (with

RTC) V

=3.0 V

0.53 µA (with

RTC) V

=3.0 V

1. Legend:

“Y” = Yes (enable).

“O” = Optional, can be enabled/disabled by software)

“-” = Not available

2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.

3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the

peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need

it anymore.

4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup on

address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running

the HSI clock.

5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up

the HSI during reception.

Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (continued)

(1)(2)

IPs Run/Active Sleep

Low-

power

run

Low-

power

sleep

Stop Standby

Wakeup

capability

Wakeup

capability

Functional overview STM32L011x3/4

20/119 DocID027973 Rev 5

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L011x3/4 embed a nested vectored interrupt controller able to

handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

• includes a Non-Maskable Interrupt (NMI)

• provides zero jitter interrupt option

• provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved

through the hardware stacking of registers, and the ability to abandon and restart load-

multiple and store-multiple operations. Interrupt handlers do not require any assembler

wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also

significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.4 Reset and supply management

3.4.1 Power supply schemes

• V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided

externally through V

pins.

• V

SSA

, V

DDA

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively. On

TSSOP14 package, V

DDA

is internally connected to V

3.4.2 Power supply supervisor

The devices feature an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up should guarantee that 1.65 V is reached on V

at least 1 ms after it exits

the POR area.

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