STM32L073系列超低功耗MCU datasheet详解

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Functional overview STM32L073xx

16/139 DocID027096 Rev 3

Table 3. Functionalities depending on the operating power supply range

Operating power

supply range

Functionalities depending on the operating power supply range

DAC and ADC

operation

Dynamic

voltage scaling

range

I/O operation USB

= 1.65 to 1.71 V

ADC only,

conversion time

up to 570 ksps

Range 2 or

range 3

Degraded speed

performance

Not functional

= 1.71 to 1.8 V

(1)

1. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5

μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2

MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.

ADC only,

conversion time

up to 1.14 Msps

Range 1, range 2

or range 3

Degraded speed

performance

Functional

(2)

= 1.8 to 2.0 V

(1)

Conversion time

up to 1.14 Msps

Range1, range 2

or range 3

Degraded speed

performance

Functional

(2)

= 2.0 to 2.4 V

Conversion time

up to

1.14 Msps

Range 1, range 2

or range 3

Full speed operation Functional

(2)

2. To be USB compliant from the I/O voltage standpoint, the minimum V

DD_USB

is 3.0 V.

= 2.4 to 3.6 V

Conversion time

up to

1.14 Msps

Range 1, range 2

or range 3

Full speed operation Functional

(2)

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 2

32 kHz to 4.2 MHz (0ws) Range 3

Functional overview STM32L073xx

20/139 DocID027096 Rev 3

3.3 ARM

Cortex

-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a

broad range of embedded applications. It offers significant benefits to developers, including:

 a simple architecture that is easy to learn and program

 ultra-low power, energy-efficient operation

 excellent code density

 deterministic, high-performance interrupt handling

 upward compatibility with Cortex-M processor family

 platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor

core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional

energy efficiency through a small but powerful instruction set and extensively optimized

design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-

bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded ARM core, the STM32L073xx are compatible with all ARM tools and

software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L073xx embed a nested vectored interrupt controller able to

handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

 includes a Non-Maskable Interrupt (NMI)

 provides zero jitter interrupt option

 provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved

through the hardware stacking of registers, and the ability to abandon and restart load-

multiple and store-multiple operations. Interrupt handlers do not require any assembler

wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also

significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

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