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High Speed Digital Design Principles
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Figure 1. Sample Customer Board with a clean design
Figure 1 illustrates a design which employs a good architecture and layout
method by following the product PDG.
“Schematic”-ally Correct
It is important to check the schematics against the guidelines provided for
various high speed busses (Clock signals, DDR2, DDR3, PCI express etc) and
to correct the errors. It is also imperative that all the pull up/pull down
resistors are verified for the value and the voltages provided to the devices
are checked. Additional information on schematic design and the process of
checking schematics is available in the
Embedded Design Center (EDC).
Schematics need to be thoroughly checked since layout is directly cascaded
down from the schematics. A small error in the schematic will be harder to
find in layout. Layout engineers do not check for the right values; they layout
the schematic reports.