ES7243E：高性能音频编解码器芯片技术规格

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"ES7243E是一款高性能立体声音频ADC，适用于各种音频应用，如麦克风阵列、条形音箱、音频接口、数字电视、A/V接收器、DVR和NVR。该芯片提供了高信噪比、低总谐波失真加噪声以及低噪声增益放大器，确保了出色的音频质量。它支持24位、8至48kHz的采样频率，并兼容I2S/PCM主从串行数据端口，还支持多达16通道的TDM。此外，ES7243E具有自动电平控制(ALC)、噪声门功能，以及对数字麦克风的支持。其低功耗特性使其在电池供电或节能应用中表现出色。" ES7243E音频编解码器是音频处理领域的核心组件，其主要特性包括以下几个方面： 1. 高性能多比特ΔΣ音频ADC：采用先进的ΔΣ调制技术，提供101dB的信噪比和-90dB的总谐波失真加噪声(THD+N)，确保了高质量的音频输出。 2. 低噪声增益放大器：内置低噪声PGA，有助于减少信号处理过程中的噪声干扰，提高音频信号的纯净度。 3. 多通道支持：支持TDM（时间分复用）模式，最多可达16个通道，适合处理复杂的多声道音频系统。 4. 灵活的采样频率：适应256/384Fs，USB12/24MHz以及其他非标准音频系统时钟，满足不同应用的需求。 5. 自动电平控制与噪声门：ALC功能可以自动调整音频电平，防止过载，而噪声门则能消除背景噪声，优化音频体验。 6. 数字麦克风支持：芯片内置对数字麦克风的支持，方便集成到现代数字音频系统中。 7. 接口多样性：支持I2C、SPI和UART等接口，便于与其他微控制器或处理器通信，进行配置和控制。 8. 小尺寸和低功耗：采用QFN-20封装，尺寸紧凑，同时具备低待机功耗和工作功耗，适合便携式和节能设备。在应用电路中，ES7243E通常会连接到微控制器或其他音频处理单元，通过I2C接口进行配置和控制。数字音频接口如SDOUT/AD2、SCLK、LRCK和MCLK用于传输和同步音频数据。TDM接口允许同时处理多个音频通道。CCLK和CDATA用于提供和同步内部工作时钟。 ES7243E是一款集成了高级音频处理功能和高效能特性的编解码器，广泛应用于需要高质量音频处理的各类电子设备中。其丰富的功能、良好的兼容性和低功耗设计使其成为音频系统设计的理想选择。

Everest Semiconductor Confidential ES7243E

Revision 2.0 6 June 2019

Latest datasheet: www.everest-semi.com

or info@everest-semi.com

3. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports standard audio clocks (64Fs, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks

(12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc).

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and

SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the

system clock with specific rates. In master mode, LRCK and SCLK are derived internally from

device master clock.

4. MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard I

C micro-controller configuration interface. External micro-

controller can completely configure the device through writing to internal configuration

registers.

C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock

line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in

Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on

a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being

transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull

the CDATA low. The transfer rate of this interface can be up to 400 kbps.

A master controller initiates the transmission by sending a “start” signal, which is defined as a

high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.

It is a seven-bit chip address followed by a RW bit. The chip address must be 0010 x, where x

equals AD2 AD1 AD0. The RW bit indicates the slave data transfer direction. Once an

acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the

direction specified by the RW bit. The master can terminate the communication by generating a

“stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high.

In I

C interface mode, the registers can be written and read. The formats of “write” and “read”

instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you

must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the

Table 1 Write Data to Register in I

C Interface Mode

Chip Address R/W Register Address Data to be written

start

0010 AD2 AD1 AD0

ACK

RAM

ACK

DATA

ACK

Stop

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