7 CPU
Page 18
7 CPU
The ARM
®
Cortex
®
-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb
®
-2
technology) that implements a superset of 16 and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing, including:
• Digital signal processing (DSP) instructions
• Single-cycle multiply and accumulate (MAC) instructions
• Hardware divide
• 8- and 16-bit single instruction multiple data (SIMD) instructions
• Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can be
enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache
on page 29. The section Electrical specification on page 18 shows CPU performance parameters
including wait states in different modes, CPU current and efficiency, and processing power and efficiency
based on the CoreMark
®
benchmark.
7.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in
turn will trigger the FPU interrupt.
See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within
the floating-point status and control register (FPSCR) needs to be cleared. For more information about the
FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark
™
benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol Description Min. Typ. Max. Units
W
FLASH
CPU wait states, running CoreMark from flash, cache disabled 2
W
FLASHCACHE
CPU wait states, running CoreMark from flash, cache enabled 3
W
RAM
CPU wait states, running CoreMark from RAM 0
I
DDFLASHCACHE
CPU current, running CoreMark from flash, cache enabled, LDO 6.5 mA
I
DDFLASHCACHEDCDC
CPU current, running CoreMark from flash, cache enabled,
DCDC 3V
3.6 mA
I
DDFLASH
CPU current, running CoreMark from flash, cache disabled, LDO mA
I
DDFLASHDCDC
CPU current, running CoreMark from flash, cache disabled,
DCDC 3V
mA
I
DDRAM
CPU current, running CoreMark from RAM, LDO mA
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