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三星eMMC4.5协议详解与开发指南
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更新于2024-07-24
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"eMMC4.5协议是JEDEC(固态技术协会)制定的一个嵌入式多媒体卡(Embedded Multi-Media Card)的电气标准,旨在规范4.5版本设备的相关技术规格。这份文档对于开发三星eMMC产品具有很高的参考价值,能够帮助开发者理解和实现eMMC4.5协议中的各项功能和特性。"
eMMC4.5协议是固态存储设备领域的一个重要标准,主要应用于移动设备如智能手机、平板电脑等,它定义了嵌入式多媒体卡的电气接口、命令集、数据传输方式以及错误处理机制等关键部分。以下是eMMC4.5协议的一些核心知识点:
1. **接口规范**:eMMC4.5协议在物理层上通常采用HS200高速模式,支持高达200MB/s的数据传输速率,比之前的版本有了显著提升。同时,它采用了DDR(Double Data Rate)模式,能够在时钟的上升沿和下降沿同时传输数据,进一步提高了数据吞吐量。
2. **命令集**:eMMC4.5协议定义了一套丰富的命令集,包括读写命令、状态查询命令、擦除命令等,以满足不同操作需求。例如,CMD16用于设置块长度,CMD51用于读取器件的SRAM信息,CMD27用于写单个块等。
3. **错误处理**:协议中包含了错误检测和恢复机制,如CRC(Cyclic Redundancy Check)用于检测数据传输错误,以及自动重试和错误纠正功能,确保数据的正确性和可靠性。
4. **电源管理**:考虑到移动设备的电池寿命,eMMC4.5协议提供了多种电源模式,包括低功耗模式和深度休眠模式,以便设备在不同工作状态下优化能耗。
5. **安全性**:协议还涉及到了数据安全相关功能,如加密和安全分区,以保护存储在eMMC上的敏感信息。
6. **硬件兼容性**:eMMC4.5协议保持与早期版本的向后兼容,允许设备制造商在不改变硬件接口的情况下升级固件。
7. **主机控制器接口**:eMMC与主机之间的通信是通过一个专用的控制器进行的,这个控制器负责协议转换、数据缓冲和错误处理等功能,简化了主机系统的设计。
8. **性能测试**:协议规定了一系列的性能测试方法,包括读写速度、随机访问性能等,以验证设备是否符合标准要求。
eMMC4.5协议是现代移动设备中存储技术的重要组成部分,其详细的技术规范为开发者提供了实现高效、可靠且节能的存储解决方案的基础。通过深入理解并遵循这一协议,开发者可以设计出更符合市场需求的产品。
JEDEC Standard No. 84-B45
-xii-
EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (4.5 Device)
List of Tables (cont'd)
Page
Table 33 - RTC_INFO_TYPE Field Description ....................................................................................... 83
Table 34 - Command Format ...................................................................................................................... 88
Table 35 - Supported Device command classes (0–56) .............................................................................. 89
Table 36 - Basic commands (class 0 and class 1) ....................................................................................... 90
Table 37 - Block-oriented read commands (class 2) ................................................................................... 91
Table 38 - Class 3 commands ..................................................................................................................... 91
Table 39 - Block-oriented write commands (class 4) ................................................................................. 92
Table 40 - Block-oriented write protection commands (class 6) ................................................................ 94
Table 41 - Erase commands (class 5) .......................................................................................................... 95
Table 42- I/O mode commands (class 9) .................................................................................................... 96
Table 43 - Lock Device commands (class 7) .............................................................................................. 96
Table 44 - Application-specific commands (class 8) .................................................................................. 96
Table 45 - Device state transitions .............................................................................................................. 97
Table 46 - R1 response ............................................................................................................................... 99
Table 47 - R2 response ............................................................................................................................... 99
Table 48 - R3 Response ............................................................................................................................ 100
Table 49 - R4 response ............................................................................................................................. 100
Table 50 - R5 response ............................................................................................................................. 100
Table 51 - Device status ............................................................................................................................ 102
Table 52 - Device Status field/command - cross reference ....................................................................... 104
Table 53 - Response 1 Status Bit Valid .................................................................................................... 105
Table 54 - Timing Parameters ................................................................................................................... 116
Table 55 – Timing Parameters for HS200 mode ...................................................................................... 117
Table 56 - H/W reset timing parameters ................................................................................................... 120
Table 57 - OCR register definitions .......................................................................................................... 121
Table 58 - CID Fields ............................................................................................................................... 122
Table 59 - Device Types ........................................................................................................................... 122
Table 60 - CSD Fields ............................................................................................................................... 124
Table 61 - CSD register structure ............................................................................................................. 125
Table 62 - System specification version ................................................................................................... 125
Table 63 - TAAC access-time definition .................................................................................................. 125
Table 64 - Maximum bus clock frequency definition ............................................................................... 126
Table 65 - Supported Device command classes ........................................................................................ 126
Table 66 - Data block length ..................................................................................................................... 127
Table 67 - DSR implementation code table .............................................................................................. 127
Table 68 - V
DD
(min) current consumption ............................................................................................... 128
Table 69 - V
DD
(max) current consumption .............................................................................................. 128
Table 70 - Multiplier factor for device size .............................................................................................. 129
Table 71 - R2W_FACTOR ....................................................................................................................... 130
Table 72 - File formats .............................................................................................................................. 131
Table 73 - ECC type ................................................................................................................................. 131
Table 74 - CSD field command classes .................................................................................................... 132
Table 75 - Extended CSD ......................................................................................................................... 134
JEDEC Standard No. 84-B45
-xiii-
EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (4.5 Device)
List of Tables (cont'd)
Page
Table 76 - Device-supported command sets ............................................................................................. 138
Table 77 - HPI features ............................................................................................................................. 138
Table 78 - Background operations support ............................................................................................... 138
Table 79 - Context Management Context Capabilities ............................................................................. 139
Table 80 - Extended CSD Register Support ............................................................................................. 140
Table 81 - Generic Switch Timeout Definition ......................................................................................... 140
Table 82 - Power off long switch timeout definition ................................................................................ 140
Table 83 - Background operations status .................................................................................................. 141
Table 84 - Correctly programmed sectors number ................................................................................... 141
Table 85 - Initialization Time out value .................................................................................................... 141
Table 86 - TRIM/DISCARD Time out value ........................................................................................... 142
Table 87 - SEC Feature Support ............................................................................................................... 142
Table 88 - Boot information ..................................................................................................................... 143
Table 89 - Boot partition size .................................................................................................................... 143
Table 90 - Access size ............................................................................................................................... 144
Table 91 - Superpage size ......................................................................................................................... 144
Table 92 - Erase-unit size ......................................................................................................................... 144
Table 93 - Erase timeout values ................................................................................................................ 145
Table 94 - Reliable write sector count ...................................................................................................... 145
Table 95 - Write protect group size .......................................................................................................... 145
Table 96 - S_C_VCC, S_C_VCCQ timeout values .................................................................................. 146
Table 97 - Sleep/awake timeout values ..................................................................................................... 146
Table 98 - R/W access performance values .............................................................................................. 147
Table 99 - Power classes ........................................................................................................................... 148
Table 100 - Partition switch timeout definition ........................................................................................ 149
Table 101 - Out-of-interrupt timeout definition ........................................................................................ 149
Table 102 – Supported Driver Strengths ................................................................................................... 149
Table 103 - Device types .......................................................................................................................... 150
Table 104 - CSD register structure ........................................................................................................... 150
Table 105 - Extended CSD revisions ........................................................................................................ 150
Table 106 - Standard MMC command set revisions ................................................................................. 151
Table 107 - Power class codes .................................................................................................................. 151
Table 108 - HS_TIMING (timing and driver strength) ............................................................................ 152
Table 109 - HS_TIMING values .............................................................................................................. 152
Table 110 - Bus mode values .................................................................................................................... 152
Table 111 - Erased memory content values .............................................................................................. 152
Table 112 - Boot configuration bytes ....................................................................................................... 153
Table 113 - Boot config protection ........................................................................................................... 154
Table 114 - Boot bus configuration .......................................................................................................... 155
Table 115 - Bus Width and Timing Mode Transition ............................................................................... 156
Table 116- ERASE_GROUP_DEF .......................................................................................................... 156
Table 117 - BOOT area write protection .................................................................................................. 157
Table 118 - User area write protection ...................................................................................................... 159
JEDEC Standard No. 84-B45
-xiv-
EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (4.5 Device)
List of Tables (cont'd)
Page
Table 119 - FW Update Disable ............................................................................................................... 160
Table 120 - RPMB Partition Size ............................................................................................................. 160
Table 121 - Write reliability setting .......................................................................................................... 161
Table 122 - Write reliability parameter register ........................................................................................ 162
Table 123 - Background operations enable ............................................................................................... 162
Table 124 - H/W reset function ................................................................................................................. 163
Table 125 - HPI management ................................................................................................................... 163
Table 126 - Partitioning Support ............................................................................................................... 164
Table 127 - Max. Enhanced Area Size ..................................................................................................... 164
Table 128 - Partitions Attribute ................................................................................................................ 165
Table 129 - Partition Setting ..................................................................................................................... 165
Table 130 - General Purpose Partition Size .............................................................................................. 166
Table 131 - Enhanced User Data Area Size .............................................................................................. 166
Table 132 - Enhanced User Data Start Address ........................................................................................ 167
Table 133 - Secure Bad Block management ............................................................................................. 167
Table 134 - Initialization Time out value .................................................................................................. 169
Table 135 – Class 6 usage ......................................................................................................................... 169
Table 136 - EXCEPTION_EVENTS_CTRL[56] ..................................................................................... 170
Table 137 - EXCEPTION_EVENTS_CTRL[57] ..................................................................................... 170
Table 138 - EXCEPTION_EVENTS_STATUS[54] ................................................................................ 170
Table 139 - EXCEPTION_EVENT_STATUS[55] .................................................................................. 170
Table 140 - First Byte EXT_PARTITIONS_ATTRIBUTE[52] .............................................................. 171
Table 141 - Second Byte EXT_PARTITIONS_ATTRIBUTE[53] .......................................................... 171
Table 142 - CONTEXT_CONF configuration format .............................................................................. 172
Table 143- Packed Command Status Register .......................................................................................... 172
Table 144 - Valid POWER_OFF_NOTIFICATION values ..................................................................... 173
Table 145 - Error correction codes ........................................................................................................... 174
Table 146 - DSR register content .............................................................................................................. 181
Table 147 - General operating conditions ................................................................................................. 183
Table 148 - e•MMC power supply voltage ............................................................................................... 185
Table 149 - e•MMC voltage combinations ............................................................................................... 185
Table 150 - Capacitance ............................................................................................................................ 186
Table 151 - Open-drain bus signal level ................................................................................................... 187
Table 152 - Push-pull signal level—high-voltage e•MMC ...................................................................... 187
Table 153 - Push-pull signal level—1.65-1.95 VCCQ voltage Range ..................................................... 188
Table 154 - Push-pull signal level—1.1V-1.3V VCCQ range e•MMC .................................................... 188
Table 155 – I/O driver strength types ....................................................................................................... 189
Table 156 - Driver Type-0 AC Characteristics ........................................................................................ 190
Table 157 - High-speed Device interface timing ...................................................................................... 191
Table 158 - Backward-compatible Device interface timing ..................................................................... 192
Table 159 - High-speed dual rate interface timing .................................................................................... 193
Table 160 - HS200 Clock signal timing .................................................................................................... 194
Table 161 - HS200 Device input timing ................................................................................................... 196
JEDEC Standard No. 84-B45
-xv-
EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (4.5 Device)
List of Tables (cont'd)
Page
Table 162 - Output timing ......................................................................................................................... 197
Table 163 - e•MMC host requirements for Device classes ....................................................................... 199
Table 164 - New Features List for device type ......................................................................................... 200
Table 165 - Macro commands .................................................................................................................. 202
Table 166 - Forward-compatible host interface timing ............................................................................. 213
Table 167 - XNOR values ......................................................................................................................... 217
Table 168 - Package Case Temp (Tc) per current consumption ............................................................... 222
JEDEC Standard No. 84-B45
-xvi-
Foreword
This standard has been prepared by JEDEC and the MMC Association, hereafter referred to as MMCA.
JEDEC took the basic MMCA specification and adopted it for embedded applications, calling it
“e•MMC.”
The purpose of this standard is the definition of the e•MMC Electrical Interface, its environment and
handling. It provides guidelines for systems designers. The standard also defines a tool box (a set of
macro functions and algorithms) that contributes to reducing design-in effort.
Introduction
The e•MMC is a managed memory capable of storing code and data. It is specifically designed for mobile
devices. The e•MMC is intended to offer the performance and features required by mobile devices while
maintaining low power consumption. The e•MMC device contains features that support high throughput
for large data transfers and performance for small random data more commonly found in code usage. It
also contains many security features.
e•MMC communication is based on an advanced 10-signal bus. The communication protocol is defined
as a part of this standard and referred to as the e•MMC mode.
The e•MMC standard only covers embedded devices, however, the protocol and commands were
originally developed for a removable Device. The spec has been updated to remove references to the
removable Device but some functions remain to support backward compatibility.
As used in this document, “shall” or “will” denotes a mandatory provision of the standard. “Should”
denotes a provision that is recommended but not mandatory. “May” denotes a feature whose presence
does not preclude compliance, which may or may not be present at the option of the implementer.
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