PDP-11_40处理器手册：Unix V6开发的关键资源

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PDP-11_40处理器手册（1972）是一份由Digital Equipment Corporation (DEC) 出版的专业文档，它详细介绍了当时流行的PDP-11系列计算机系统的技术特性、架构和软件支持。该手册特别关注的是Unix V6开发所使用的PDP-11计算机，这在当时是一个重要的技术平台。首先，手册在第一章“简介”中概述了PDP-11_40的主要特征。1.1节讨论了系统的通用特性，包括其高效能的UNIBUS总线系统，这是一种标准接口，允许不同硬件组件间的无缝通信。UNIBUS设计允许模块化扩展，增强了系统的灵活性。 1.2节着重于中央处理器，介绍了它的基本结构，如寄存器体系、浮点运算能力和内存管理功能。处理器具有通用寄存器用于数据处理，同时提供处理器状态字，用于跟踪指令执行状态。栈限制寄存器则支持高效的堆栈操作。在1.3节，手册探讨了外部设备和选项，涵盖了输入/输出设备（如纸带机和磁盘驱动器）以及不同类型的总线扩展选项，以适应多样化的应用场景需求。此外，1.4节涉及软件部分，提到了用于纸带输入的专用软件以及基于磁盘的操作系统软件，如Unix V6，这是当时的主流操作系统之一。同时，手册还介绍了高级编程语言的支持，以便开发人员编写更复杂的程序。章节2“系统架构”进一步深入，2.1和2.2部分详细描述了系统架构，包括双向数据线设计和主从关系，确保了系统之间的可靠通信。中央处理器的详细内核结构在2.3节详述，包括核心寄存器和控制逻辑。此外，自动优先级中断系统在2.6.1节有所提及，强调了中断处理对于实时性和效率的重要性，以及如何有效地利用它们。这份PDP-11_40处理器手册提供了关于70年代中期PDP-11系列计算机的核心技术信息，对于理解那个时代的计算机设计思想和技术实践具有重要意义。无论是硬件设计、系统通信、还是软件支持，都是那个时代信息技术发展的重要组成部分。

Octal Representation

:-:--1~5114

12l11

e 1

&15

4 3 [ 2 1 o I

PDP-11

word

~~-------_!---)~~

I I

~~---------~

D D D D D D 6-digit octal

The 16-bit

PDP-11

word can

represented conveniently

a 6-digit

octal word. Bit 15, the Most Significant

Bit

(MSB), is used directly

the

MSB

the octal word. The other 5 octal digits are formed from

the

corresponding groups

3 bits in the binary word.

When

extended address

18 bits is used (shown later in the Hand-

book),

the

MSB

the octal word is formed from bits 17, 16, and 15.

For unsigned numbers, the correspondence between

decimal and octal is:

Decimal

(216-1)=

65,535

(218-1)=262,143

2's

Complement Numbers

Octal

000000

177777

777777

(16-bit

limit)

(18-bit

limit)

this

system, the

first

bit

(bit

15) is used

indicate

the

sign;

O=positive

1=negative

For positive numbers, the other 15 bits represent the magnitude directly;

for

negative numbers, the magnitude is

the

2's

complement

the

re-

maining 15 bits. (The

2's

complement is equal

the

1's

complement

plus

one.) The ordering

numbers is shown below:

Decimal

2's

Complement (Octal)

Sign

Bit

Magnitude Bits

largest positive

+32,767

77777

+32,766

77776

00001

00000

-1

77777

-2

77776

-32,767

00001

most negative

-32,768

00000

1-8

CHAPTER

SYSTEM

ARCHITECTURE

2.1

SYSTEM

DEFINITION

The PDP-11/40 is a 16-bit, general-purpose, parallel logic

computer

using

2's

complement arithmetic. The processor can directly address

32,768

16-bit

words

65,536

8-bit

bytes.

The

Central Processing

Unit

performs all

arithmetic

and logical opera-

tions

required in

the

system. A Floating Point

Unit

mounts

integrally

into

the

Central Processor as does a Memory Management

Unit

which pro-

vides a full memory managemnt

facility

through relocation and protec-

tion.

The PDP-11/40 hardware has been optimized towards a

multi-program-

ming

environment and the processor therefore operates in two modes

(Kernel and User). By

taking

full advantage

this

feature, a software

operating system can insure

that

no user (who is operating in User

mode) can cause a

failure (crash)

the

entire system. Full control

the

entire system is retained

the console

by an operator who is in

Kernel mode.

2.2 UNIBUS

The UNIBUS is a single, common path

that

connects the central proces-

sor, memory, and all peripherals. Addresses, data, and control informa-

tion

are sent along

the

lines

the

bus.

The

form

communication is

the

same

for

every device on the UNIBUS.

The processor uses the same set

signals

communicate with mem-

ory as with peripheral devices. Peripheral devices also use

this

set

signals when communicating

with

the processor, memory

other

pe-

ripheral devices. Each device, including memory locations, processor

registers, and

peripheral device registers, is assigned an address on

the

UNIBUS. Thus, peripheral device registers may be manipulated as flex-

ibly

as core memory by the central processor. All

the

instructions

that

can

applied

data in core memory can

applied equally well

data in peripheral device registers. This is an especially powerful feature,

considering the

special capability

PDP-11 instructions

process data

in any memory

location as though

were an accumulator.

2.2.1 Bidirectional

Lines

Most UNIBUS lines are bidirectional, so

that

the

same signals

that

are

received as

input

can

driven as output. This means

that

a peripheral

device register can

either read

loaded by the central processor

2-1

other

peripheral devices; thus, the same register can be used

for

both

input

and

output

functions.

2.2.2

Master-Slave Relation

Communication between

two

devices on

the

bus is in

the

form

master-slave relationship. At any point in time, there is one device

that

has control

the

bus. This controlling device is termed

the

"bus

mas·

ter".

The master device controls the bus when communicating

with

another device on

the

bus, termed

the

"slave".

A typical example

this

relationship is

the

processor, as master, fetching an instruction

from

memory

(which is always a slave). Another example is

the

disk, as

master,

transferring

data

memory, as slave. Master-slave relation·

ships are dynamic. The processor,

for

example, may pass bus control

a disk. The disk,

master, could then communicate

with

a slave

memory bank.

Since the UNIBUS is used by

the

processor and all 1/0 devices, there is

priority

structure

determine which device gets control

the

bus.

Every device on the

UNIBUS which is capable

becoming bus master

assigned a priority. When two devices, which are capable

becoming

a bus master, request use

the

bus simultaneously,

the

device with

the

higher

priority

will receive control.

2.2.3

Interlocked Communication

Communication on the

UNIBUS is interlocked so

that

for

each control

signal

issued by

the

master device, there

must

a response

from

the

slave in order

complete

the

transfer. Therefore, communication is

independent

the

physical bus length (as

far

timing

is concerned)

and the response

time

the master and slave devices. This asynchron·

ous operation

precludes

the

need

for

synchronizing with, and waiting

for,

clock pulses. Thus, each device is allowed

operate at its

maximum

possible speed.

2.3

CENTRAL

PROCESSOR

The

PDP·ll/40

performs all

arithmetic

and logical operations required

the

system.

also acts as

the

arbitration

unit

for

UNIBUS control by

regulating bus requests and transferring control

the

bus

the

re·

questing device with

the

highest priority.

Space is provided

within

the

central processor

for

the

following options:

Extended

Instruction Set

Floating

Point

Unit

Memory Management

Unit

Programmable Stack

Limit

The machine operates in

two

modes; Kernel and User. When

the

machine

is in

Kernel mode a program has complete control

the machine;

when in User mode

the

processor is inhibited

from

executing certain

instructions

and can

denied direct access

the peripherals on

the

system. This hardware feature can be used

provide complete execu·

tive protection in a multi-programming environment.

The

central processor contains 8 general registers which can be used

accumulators, index registers,

as stack pointers. A stack, as used

2·2

normally used only

for

addressing purposes and not as an accumulator

for

arithmetic

operations.

The

the

Processor Stack Pointer indicat·

ing

the

last entry in

the

appropriate stack (a common temporary storage

area with

"Last-in First-Out" characteristics). The two stacks (with the

Memory Management option) are

called

the

Kernel Stack and

the

User

Stack. When

the

Central Processor is operating in Kernel mode

uses

the

Kernel Stack and in User mode,

the

User Stack. When an interrupt

trap

occurs,

the

PDP·ll/40

automatically saves its current status

the

Processor Stack selected by

the

service routine. This stack·based

architecture facilitates reentrant programming.

2.3.2

Processor Status Word

14131211

CURRENT

M~t

..______.._.,}

MOOE"t'-----'-

PRIORITY--------------_J

CONDITION

CODES

*MODE: 00•KERNEL

=USER

Figure 2-2 Processor Status Word

3 2 I 0

The Processor Status Word (PS), located

location 777776, contains

information on

the

current status

the PDP-11/40. This information in-

cludes

the

current processor priority: current and previous operational

modes;

the

condition codes describing the results

the

last instruction;

and an indicator

for

detecting the execution

an instruction

trapped during program debugging.

Modes

(with

Memory Management Option)

Mode information

includes

the

present mode, either User

Kernel (bits

15, 14) and

the

mode

the

machine was in prior

the

last interrupt

trap

(bits 13, 12).

The two modes permit a

fully

protected environment

for

a multi-

programming system by providing

the

user with two

distinct

sets

Processor Stacks and Memory Management Registers

for

memory map-

ping. In User mode a program is inhibited from executing a

"HALT"

in-

struction and

the

processor will

trap

through location

an attempt

is made

execute

this

instruction. Furthermore,

the

processor will

ignore

the

"RESET" instruction. In Kernel mode,

the

processor will

ex-

ecute all instructions.

A program operating in

Kernel mode can map users' programs anywhere

in core and

thus

explicitly protect key areas (including

the

device reg-

isters and the Processor Status Word) from

the

User operating environ-

ment.

2-4

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