Serial ATA 2.6规范详解：高速串行ATA接口技术

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"Serial ATA Revision 2.6 Gold" 是串行ATA（SATA）接口规范的一个重要版本，由Serial ATA International Organization (SATA-IO)发布，旨在更新和改进SATA技术，以满足高性能存储需求。这个版本的规格书是在2007年2月15日发布的，涉及的主要参与者包括Dell、HP、Hitachi Global Storage Technologies、Intel、Seagate Technology和Vitesse Semiconductor Corporation等业界知名公司。 SATA 2.6规范是针对ATA驱动器的一项关键技术升级，它主要关注以下几个方面： 1. **速度提升**：SATA 2.6在SATA 2.5的基础上进一步提升了数据传输速率。虽然具体速率未在摘要中提及，但SATA 2.x系列通常支持300MB/s（SATA 2.0）和600MB/s（SATA 2.5），这显著提高了硬盘和光驱的数据交换效率。 2. **功能增强**：SATA 2.6可能包含了更多增强功能，如Port Multiplier（端口倍增器）和Port Selectors（端口选择器），这些功能允许单个SATA接口控制多个硬盘，简化了系统设计并降低了成本。 3. **错误处理与可靠性**：规范可能包含更严格的错误检测和纠正机制，如高级错误报告，以确保数据传输的准确性。此外，热插拔功能的优化使得设备可以在系统运行时安全地接入或移除。 4. **电源管理**：SATA 2.6可能改进了电源管理标准，比如支持待机模式和休眠模式，以降低设备的功耗，符合绿色节能的需求。 5. **兼容性**：新版本的规格通常会保持向后兼容，确保新设备可以与旧的SATA控制器和母板协同工作，避免升级带来的兼容性问题。 6. **协议扩展**：SATA 2.6可能引入新的命令集和协议，例如NCQ（Native Command Queuing，原生指令队列）的改进，提高硬盘的内部调度效率，从而提升整体系统性能。 7. **知识产权声明**：摘要中的免责声明指出，此规格书的提供不附带任何保证，使用者需自行承担可能侵犯知识产权的风险，且不自动授予任何许可权。 SATA 2.6规范对于理解和支持当时的高性能存储解决方案至关重要，它不仅提升了数据传输速度，还增强了系统功能和可靠性。对于硬件开发者和系统集成商来说，了解并遵循这个规格是构建高效、可靠存储系统的前提。

Figure 217 – Device Activity LEDs with Separate Wires............................................................. 493

Figure 218 – Device Activity LEDs with Ribbon Cable................................................................ 494

Figure 219 – Device Activity LEDs in a Storage Subsystem....................................................... 495

Figure 220 – Software reset to control port result values............................................................ 496

Figure 221 – Port Multiplier Signature ......................................................................................... 498

Figure 222 – SActive register definition....................................................................................... 504

Figure 223 – SNotification register definition............................................................................... 505

Figure 224 – Error handling architecture..................................................................................... 507

Figure 225 – Port Multiplier Overview ......................................................................................... 517

Figure 226 – Port Selector Overview........................................................................................... 547

Figure 227 – Example Failover Application with Two Hosts ....................................................... 548

Figure 228 – Port selection signal based on assertion of COMRESET to assertion of following

COMRESET ........................................................................................................................ 550

Figure 229 – Complete port selection signal consisting of two sequences with requisite inter-reset

spacings............................................................................................................................... 551

Figure 230 – Control State Machine............................................................................................ 553

Figure 231 – Phy Block Diagram................................................................................................. 554

Figure 232 – Concept summary interconnect structure .............................................................. 584

Figure 233 – An example of signal connections with one I/O Controller..................................... 585

Figure 234 – Example of signal connections with two I/O Modules ............................................ 587

Figure 235 – High Speed Channels – Configuration 0................................................................ 588

Figure 236 – High-Speed Channels – Configuration 1 ............................................................... 588

Figure 237 – Low Speed Channels ............................................................................................. 589

Figure 238 – Interconnect Channels ........................................................................................... 589

Figure 239 – I/O Controller Module Connector Rendering.......................................................... 590

Figure 240 – Connector Pin Layout and Pin Lengths.................................................................. 591

Figure 241 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 592

Figure 242 – Side View of Connector.......................................................................................... 592

Figure 243 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 594

Figure 244 – I/O Controller Module Connector Locations on 2xWide I/O Module ...................... 595

Serial ATA Revision 2.6 xix

TABLE OF TABLES

Table 1 – State Table Cell Description .......................................................................................... 41

Table 2 – Usage Model Descriptions............................................................................................. 46

Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 76

Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 85

Table 5 – Housing and contact electrical parameters, test procedures, and requirements .......... 89

Table 6 – Mechanical test procedures and requirements ............................................................. 90

Table 7 – Environmental parameters, test procedures, and requirements ................................... 91

Table 8 – Additional requirement................................................................................................... 91

Table 9 – Connector test sequences............................................................................................. 92

Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence ............. 113

Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 114

Table 12 – Slimline Connector Location References .................................................................. 116

Table 13 – Slimline Device plug connector pin definition ............................................................ 121

Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 128

Table 15 – Multilane Pin Assignments ........................................................................................ 142

Table 16 – Internal Cable / Connector Measurement Parameter and Requirements................. 146

Table 17 – External Single Lane Cable / Connector Measurement Parameter and Requirements

............................................................................................................................................. 146

Table 18 – Limited External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 19 – Extended External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 20 – Common Interconnect Measurement Procedure Methodologies.............................. 150

Table 21 – Interconnect Test Methodologies / Procedures......................................................... 151

Table 22 – Power segment pin P11 activity signal electrical parameters ................................... 157

Table 23 – Host activity signal electrical parameters .................................................................. 157

Table 24 – Activity signal functional states.................................................................................. 158

Table 25 – Host staggered spin-up control electrical requirements ............................................ 159

Table 26 – Comparator voltages for alternate example presence detection circuit .................... 162

Table 27 – General Specifications............................................................................................... 173

Table 28 – Transmitter Specifications ......................................................................................... 174

Table 29 – Transmitted Signal Requirements ............................................................................. 175

Table 30 – Receiver Specifications ............................................................................................. 177

Table 31 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 178

Table 32 – OOB Specifications ................................................................................................... 180

Table 33 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 199

Table 34 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 200

Table 35 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 201

Table 36 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 201

Table 37 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 202

Table 38 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+..................... 203

Table 39 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 204

Table 40 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 204

Table 41 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 205

Table 42 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 205

Table 43 – Composite-Bit Pattern (COMP) Starting with RD–.................................................... 206

Table 44 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 208

Table 45 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 225

Table 46 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 226

Table 47 – OOB Signal Times..................................................................................................... 263

Table 48 – Interface Power States .............................................................................................. 273

Table 49 – State Diagram Host Phy Initialization State Machine................................................ 275

Table 50 – State Diagram Device Phy Initialization State Machine ............................................ 279

Table 51 – Bit Designations......................................................................................................... 290

Table 52 – Conversion Examples................................................................................................ 291

Table 53 – 5B/6B Coding ............................................................................................................ 293

Table 54 – 3B/4B Coding ............................................................................................................ 293

Table 55 – Encoding Examples................................................................................................... 294

Table 56 – Valid Data Characters ............................................................................................... 295

Table 57 – Valid Control Characters ........................................................................................... 299

Table 58 – Single Bit Error with Two Character Delay ................................................................ 301

Table 59 – Single Bit Error with One Character Delay ................................................................ 301

Table 60 – Description of Primitives ............................................................................................ 303

Table 61 – Primitive Encoding..................................................................................................... 304

Table 62 – CONT

Usage Example ............................................................................................ 306

Table 63 – Example of Components of a Round Trip Delay....................................................... 309

Table 64 – SRST Write from Host to Device Transmission Breaking Through a Device to Host

Data FIS............................................................................................................................... 310

Table 65 – Command Shadow Register Block Register Transmission Example ....................... 310

Table 66 – Data from Host to Device Transmission Example..................................................... 311

Table 67 – State Diagram Link Idle ............................................................................................. 314

Table 68 – State Diagram Link Transmit..................................................................................... 317

Table 69 – State Diagram Link Receive ...................................................................................... 324

Table 70 – State Diagram Link Power Mode............................................................................... 330

Table 71 – Simplified Shadow Register Block register numbering ............................................. 336

Table 72 – BIST Activate FIS Modes and Bit Settings ................................................................ 347

Table 73 – IDENTIFY DEVICE information ................................................................................. 433

Table 74 – IDENTIFY PACKET DEVICE information ................................................................. 439

Table 75 – SCR definition............................................................................................................ 500

Table 76 – SCR Definition ........................................................................................................... 500

Table 77 – State Diagram Collisions ........................................................................................... 521

Table 78 – State Diagram Hot Plug State Machine for Host Port ............................................... 523

Table 79 – State Diagram Hot Plug State Machine for Device Port............................................ 525

Table 80 – Register Values for an Unsupported Command ....................................................... 528

Table 81 – Static Information Registers ...................................................................................... 530

Table 82 – Status Information and Control Registers ................................................................. 532

Table 83 – Features Supported Registers .................................................................................. 536

Table 84 – Features Enabled Registers ...................................................................................... 537

Table 85 – Vendor Unique Registers .......................................................................................... 538

Table 86 – Phy Event Counter Registers .................................................................................... 539

Table 87 – Reserved Registers ................................................................................................... 539

Table 88 – PSCR Definition......................................................................................................... 540

Table 89 – READ PORT MULTIPLIER Command Definition ..................................................... 540

Table 90 – READ PORT MULTIPLIER Success Status Result Values ...................................... 541

Table 91 – READ PORT MULTIPLIER Error Status Result Values............................................ 542

Table 92 – WRITE PORT MULTIPLIER Command Definition .................................................... 542

Table 93 – WRITE PORT MULTIPLIER Success Status Result Values .................................... 543

Table 94 – WRITE PORT MULTIPLIER Error Status Result Values .......................................... 544

Table 95 – Port selection signal inter-reset timing requirements ................................................ 550

Table 96 – CRC and scrambler calculation example - PIO Write Command ............................. 570

Table 97 – J1, J2, J3 Pin Assignments ....................................................................................... 596

Table 98 – J4, J5, J6 Pin Assignments ....................................................................................... 596

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