![](https://csdnimg.cn/release/download_crawler_static/1476209/bg1.jpg)
Categories Features Web Edition software Subscription Edition software
General
information
Getting started Download (www.altera.com/download) and DVD (www.altera.com/dvdrequest)
Operating system support Windows: Vista (32 bit), XP (32 bit)
Windows: Vista (32/64 bit), XP (32/64 bit)
Linux: SUSE Linux Enterprise 9 (32/64 bit),
Red Hat Enterprise Linux 4 and 5 (32/64 bit)
CentOS 4 and 5 (32/64 bit)
Device
support
CPLD MAX
®
series devices: All MAX series devices: All
Low-cost FPGAs
Arria
®
GX FPGAs: All
Cyclone
®
series devices: All
Legacy families: ACEX
®
, selected
APEX II devices
Arria GX FPGAs: All
Cyclone series devices: All
Legacy families: All
High-end FPGAs
Stratix
®
IV / IV GX FPGAs: None
Stratix III FPGAs: EP3SE50, EP3SL70
Stratix II / II GX FPGAs: EP2S15, EP2SGX30
Stratix FPGAs: EP1S10
Stratix IV/ IV GX FPGAs: All
Stratix III FPGAs: All
Stratix II / II GX FPGAs: All
Stratix / GX FPGAs: All
ASIC
No
HardCopy
®
series: All
IP
Altera and partner IP Yes, including free OpenCore Plus evaluation feature
Full license IP base suite IP available for purchase
DSP: FIR, FFT, and NCO compilers; Interfaces:
SerialLite II;
Memory controllers: DDR, DDR2, DDR3, QDR II,
RLDRAM II
Design entry
SOPC Builder
Yes
Schematic entry and language support Schematic entry, Verilog, VHDL, and SystemVerilog
Design
environment
Tcl scripting, command line support
Yes
Implementation
and
optimization
Incremental compilation and team-based
design
No Yes
Multiprocessor support
No Yes
Physical synthesis optimizations
Yes
Design space explorer
Yes
Chip planner
Yes
Live I/O checking
Yes
Timing-driven placement
Yes
TimeQuest timing analyzer and optimization
advisor
Yes
Synopsys Design Constraint (SDC) format
support
Yes
Early power estimator Available to download on www.altera.com for no cost
PowerPlay power analysis and optimization
Yes
Verification
and debug
ModelSim
®
-Altera simulator ModelSim-Altera Web Edition ModelSim-Altera Edition
SignalTap
®
II logic analyzer Available with TalkBack enabled Yes
SignalProbe feature Available with TalkBack enabled Yes
Embedded logic analyzer interface
Yes
RTL viewer and technology map viewer Yes
Pin planner Yes
System design
software
Nios II Embedded Design Suite Free for both versions of Quartus II software
DSP Builder Sold as an option for both versions of Quartus II software
Third-party
support
EDA partners
Altera offers third-party support for synthesis, functional and timing simulation, static timing analysis,
board-level simulation, signal integrity analysis, and formal verification
Altera Quartus II software v8.1 —
Subscription Edition vs. Web Edition
Copyright © 2008 Altera Corporation. All rights reserved. Altera, e Programmable Solutions Company, the stylized Altera logo, specic device designations, and all other words and logos that are identied as trademarks and/or service marks
are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. ModelSim is a registered trademark of Mentor Graphics Corporation. All other product or service names are the property of
their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specications
in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for
products or services. October 2008; PDF only SA-01010-6.0