Xilinx Spartan-3 FPGA配置指南详解

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"FPGA Spartan 3 系列配置用户指南是针对Xilinx公司的Spartan-3 Generation FPGA家族的详细操作手册，包括Extended Spartan-3A、Spartan-3E和Spartan-3 FPGA系列。该文档版本为UG332(v1.6)，发布日期为2009年10月26日。本指南旨在帮助用户理解并进行FPGA的配置过程，以配合Xilinx硬件设备进行设计开发。" 本文档详细介绍了FPGA Spartan 3系列的配置流程和方法，适用于那些希望在设计中使用这些器件的工程师。Spartan-3系列是Xilinx推出的一款经济高效的FPGA产品线，提供了广泛的性能和容量选择，适用于多种应用，如嵌入式系统、数字信号处理、接口桥接等。配置FPGA是设计流程的关键步骤，它涉及到将逻辑设计（通常以VHDL或Verilog形式）编程到FPGA的内部存储器中，使器件能够执行预定的功能。Spartan-3系列支持多种配置方式，如JTAG（Joint Test Action Group）链路、串行配置、并行配置、SRAM（Static Random-Access Memory）初始化以及使用外部存储器等。用户指南将详细讲解以下核心知识点： 1. **配置架构**：解释Spartan-3 FPGA的配置架构，包括配置内存类型、配置接口和控制逻辑。 2. **配置流程**：描述从下载配置数据到FPGA的过程，包括预配置、配置和启动阶段。 3. **配置文件**：讨论如何生成和管理配置比特流文件（bitstream），这是包含了FPGA逻辑设计信息的二进制文件。 4. **配置工具**：介绍Xilinx的软件工具，如ISE (Integrated Software Environment) 或Vivado，用于设计、综合、实现和生成配置文件。 5. **JTAG配置**：详细阐述如何使用JTAG接口进行在线编程和调试。 6. **串行和并行配置**：说明这两种配置方式的优缺点，以及如何选择和实现。 7. **安全配置**：讨论如何保护配置数据不被非法复制或篡改，包括加密和版权保护机制。 8. **故障排查**：提供配置过程中可能遇到的问题及解决方案，帮助用户解决配置失败的问题。此外，文档还可能涵盖与电源管理、时序约束、多芯片同步等相关的内容，并且强调了Xilinx对于文档使用的条款和限制，包括不得未经许可复制或分发。虽然Xilinx不保证文档的准确性或对因使用文档而产生的问题负责，但他们会根据需要随时更新文档以提供最新的信息和技术支持。 "FPGA Spartan 3 系列配置用户指南"是开发人员掌握Spartan-3 FPGA配置技术的重要参考资料，无论你是初学者还是经验丰富的工程师，都能从中获取所需的信息和指导。

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Figure 3-16: Bypass Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 3-17: Select the Platform Flash Programming File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 3-18: Program the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 3-19: PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Chapter 4: Master SPI Mode

Figure 4-1: SPI Flash Configuration Interface for M25P-compatible Devices . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 4-2: SPI Flash Configuration Interface for Atmel DataFlash Devices . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 4-3: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence . . 113

Figure 4-4: If Not Using SPI after Configuration, Drive CSO_B Pin High . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 4-5: Using the SPI Flash Interface After Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-6: Daisy Chaining from SPI Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 4-7: Multiple, Identical FPGAs Programmed with the Same Bitstream . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 4-8: Using FPGA’s JTAG Test Chain to Program Attached SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 4-9: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 4-10: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-11: Set Options for a 3rd-Party SPI PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-12: Select SPI PROM Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-13: Review PROM Formatting Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-14: Add FPGA Configuration Bitstream File(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 4-15: Generate PROM File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 4-16: iMPACT Supports Direct Programming for SPI Serial Flash Memories. . . . . . . . . . . . . . . . . . 131

Figure 4-17: Select a Previously-formatted PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-18: Select a Supported SPI Flash Memory Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-19: Directly Program Supported SPI Flash PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-20: SPI PROM Programming Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-21: Indirect Programming Method Uses JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-22: Select the FPGA Bitstream File and Enable SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-23: iMPACT Uses the JTAG Clock Input TCK for Startup Clock when Programming via JTAG . . .

136

Figure 4-24: Select the SPI PROM Programming FIle

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-25: Select SPI Flash PROM Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-26: Bypass the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 4-27: iMPACT Presents JTAG Chain, Shows Attached Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 4-28: SPI PROM Programming Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 4-29: Waveforms for Serial Peripheral Interface (SPI) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 4-30: Multi-Package Layout for the M25Pxx Family on Spartan-3E Starter Kit . . . . . . . . . . . . . . . . . 142

Chapter 5: Master BPI Mode

Figure 5-1: Spartan-3E FPGA Configured from Parallel NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 5-2: Extended Spartan-3A Family FPGA Configured from Parallel NOR Flash . . . . . . . . . . . . . . . . 145

Figure 5-3: FPGA Supports x8 Interface before Configuration and Optional x16 Interface after Configuration

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Figure 5-4: Parallel Daisy Chain using BPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 5-5: Serial Daisy Chains are Only Available for Extended Spartan-3A Family BPI Mode . . . . . . . 159

Figure 5-6: Master BPI Mode Using Xilinx Parallel Platform Flash PROMs (XCFxxP). . . . . . . . . . . . . . . . . 160

Figure 5-7: Double-click Generate PROM, ACE or JTAG File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 5-8: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 5-9: Set Options for a Generic Parallel PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 5-10: Select Parallel PROM Size and Configuration Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 5-11: Select FPGA Bitstream Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 5-12: Generate Parallel PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 5-13: Parallel NOR Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On

Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 5-14: BPI Configuration Timing Waveform (Spartan-3E BPI Down mode shown) . . . . . . . . . . . . . 170

Chapter 6: Master Parallel Mode

Chapter 7: Slave Parallel (SelectMAP) Mode

Figure 7-1: Slave Parallel Mode (Spartan-3E and Extended Spartan-3A FPGA Families) . . . . . . . . . . . . . . 178

Figure 7-2: Slave Parallel Mode (Spartan-3 FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 7-3: Slave Parallel Daisy Chain for Spartan-3E/Extended Spartan-3A Family FPGAs . . . . . . . . . . . 183

Figure 7-4: Slave Parallel Daisy Chain Using Any Modern Xilinx FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 7-5: SelectMAP Continuous Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 7-6: SelectMAP Non-Continuous Data Loading with Controlled CSI_B . . . . . . . . . . . . . . . . . . . . . . 187

Figure 7-7: Non-Continuous SelectMAP Data Loading with Controlled CCLK . . . . . . . . . . . . . . . . . . . . . . 188

Figure 7-8: Configuration Abort Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 7-9: Readback Abort Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 7-10: Byte Swapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 8: Slave Serial Mode

Figure 8-1: Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Chapter 9: JTAG Configuration Mode and Boundary-Scan

Figure 9-1: JTAG Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 9-2: Typical JTAG (IEEE 1149.1) Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 9-3: Test Access Port (TAP) State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 9-4: Boundary-Scan Logic per I/O Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 9-5: Spartan-3 Generation Boundary-Scan Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 9-6: Target Interface Connector Dimensions and Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 9-7: Double-click Configure Device (iMPACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 9-8: Configure Devices Using JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 9-9: iMPACT Automatically Detects Devices on the JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 9-10: iMPACT Prompts for FPGA Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 9-11: iMPACT Automatically Adjusts FPGA Startup Clock for JTAG Configuration. . . . . . . . . . . 213

Figure 9-12: Click Bypass to Skip Platform Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

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Figure 9-13: Click Bypass to Skip CPLD Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 9-14: Double-Click Program to Configure FPGA via JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 9-15: FPGA Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Chapter 10: Internal Master SPI Mode

Figure 10-1: Spartan-3AN FPGA using Internal Master SPI Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 10-2: Spartan-3AN SPI_ACCESS Design Primitive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 10-3: Double-click Generate PROM, ACE or JTAG File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 10-4: Prepare a PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 10-5: Set Options for Spartan-3AN In-System Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 10-6: Select a Spartan-3AN FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 10-7: Specify the FPGA Configuration Bitstream(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 10-8: Review Spartan-3AN In-System Memory Formatting Settings. . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 10-9: Add FPGA Configuration Bitstream File(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 10-10: iMPACT View of the Spartan-3AN In-System Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 10-11: Generate the Spartan-3AN In-System Flash File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Chapter 11: Configuration Bitstream Generator (BitGen) Settings

Chapter 12: Sequence of Events

Figure 12-1: Spartan-3 Generation FPGA Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 12-2: FPGA Wake from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 12-3: Extended Spartan-3A Family and Spartan-3E Reset Circuitry

(Spartan-3 is similar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 12-4: FPGA Power-Up Timing Waveforms (Master Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 12-5: Clear Configuration Memory (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 12-6: Sample Control Pins (Mode Select, Variant Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 12-7: Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 12-8: Check Array ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 12-9: Load Configuration Data Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 12-10: Cyclic Redundancy Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 12-11: Startup Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 12-12: Default Start-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 12-13: Extended Spartan-3A Family, Spartan-3E FPGA Configuration Logic Conceptual Block

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 13: Configuration-Related Design Primitives

Figure 13-1: BSCAN Primitive for Extended Spartan-3A Family FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 13-2: STARTUP Primitive for Extended Spartan-3A Family and Spartan-3E FPGAs. . . . . . . . . . . . 259

Figure 13-3: CAPTURE Primitive for Extended Spartan-3A Family FPGAs (other families are similar) . 260

Figure 13-4: ICAP Primitive (only available on Extended Spartan-3A Family FPGAs) . . . . . . . . . . . . . . . . 262

Figure 13-5: DNA_PORT Primitive (only available on Extended Spartan-3A Family FPGAs) . . . . . . . . . . 263

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Chapter 14: Reconfiguration and MultiBoot

Figure 14-1: Example Spartan-3E MultiBoot Application using 1Mbyte Parallel Flash PROM . . . . . . . . . 267

Figure 14-2: Prepare a MultiBoot PROM Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 14-3: Select a PROM Supporting MultiBoot for Spartan-3E FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 14-4: Select the Configuration Direction of the First MultiBoot Image. . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 14-5: Select a PROM Size and Add It to the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 14-6: Confirm the PROM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 14-7: Select the First MultiBoot Configuration Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 14-8: Select the Second MultiBoot Configuration Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 14-9: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 14-10: PROMGen Report File (*.prm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 14-11: Spartan-3A MultiBoot Example using XC3S700A and SPI Flash . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 14-12: Prepare a MultiBoot PROM Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 14-13: Select a PROM Supporting MultiBoot for Extended Spartan-3A Family FPGAs . . . . . . . . . 284

Figure 14-14: SPI or Parallel Flash PROMs are Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 14-15: Enter a PROM Density and Specify MultiBoot Image Start Locations . . . . . . . . . . . . . . . . . . 285

Figure 14-16: Confirm PROM Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 14-17: Select the First (Default) Configuration Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 14-18: Select the Third MultiBoot Configuration Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 14-19: Generate the PROM File Using the Specified Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 14-20: Extended Spartan-3A Family MultiBoot Configuration Mode Control. . . . . . . . . . . . . . . . . . 290

Chapter 15: Protecting FPGA Designs

Figure 15-1: Setting Bitstream Generator Options from ISE Project Navigator . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 15-2: Bitstream Generator Security Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 15-3: Extended Spartan-3A Family DNA_PORT Design Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 15-4: DNA_PORT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 15-5: Possible Options for DIN Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 15-6: Extended Spartan-3A Family FPGA Configures Normally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 15-7: Extended Spartan-3A Family FPGA Authenticates the PROM Image Against Device DNA 302

Figure 15-8: Authentication Fails Using an Unauthorized Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 15-9: Spartan-3E FPGA Authentication Example using Commodity Flash PROM with Identifier 304

Figure 15-10: Spartan-3E FPGA Authenticates the PROM Image Against the PROM’s Device ID . . . . . . 305

Figure 15-11: Intelligent Host Downloads a Spartan-3A Bitstream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 15-12: Host Reads Device DNA, Generates Authentication Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 15-13: Host Writes Authentication Value to Enable FPGA Application . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 15-14: FPGA Authentication Using SHA-1 Secure EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 15-15: Extended Spartan-3A Family Device DNA Used as a Key to Protect Embedded Processing

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Chapter 16: Configuration CRC

Figure 16-1: Conceptual Overview of Post-Configuration CRC Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 16-2: UCF Constraints for Post-Configuration CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

剩余351页未读，继续阅读

Elvin

粉丝: 14
资源: 20

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