FT24C02A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(C) WRITE PROTECT (WP)
The FT24C02A devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V
IL
. Conversely all
programming functions are disabled if WP pin is connected to V
IH
or V
CC
. Read operations is not
affected by the WP pin’s input level.
MEMORY ORGANIZATION
The FT24C02A devices have 16 pages. Since each page has 16 bytes, random word addressing to
FT24C02A will require 8 bits data word addresses.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at V
IL
. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) START CONDITION
With SCL ≥ V
IH
, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL ≥ V
IH
, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command. A STOP condition after page or byte write command will trigger the chip into the
STANDBY mode after the self-timed internal programming finish.
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
ACKNOWLEDGE signal occurs on the 9th serial clock after each word.
DS3011B-page4 © 2009 Fremont Micro Devices Inc.
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