深入浅出ARM Cortex-M3汇编语言编程

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"Assembly Language Programming: ARM Cortex-M3" 在嵌入式系统的世界中，32位处理器基于的微控制器大多采用ARM设计的核心。ARM Cortex-M3便是这些设计之一，是ARM专门为微控制器应用开发的。为了创建高度优化的软件（这在嵌入式系统领域中常常是必需的），掌握汇编语言编程是必不可少的。本书“Assembly Language Programming: ARM Cortex-M3”由Vincent Mahout撰写，旨在详细介绍基于Cortex-M3架构的汇编语言编程基础，并通过大量实例进行深入讲解。对于从未接触过汇编语言的读者，这本书具有教学性质，逐步引导，定义了理解这些技术所需的概念。它不仅适合希望深入了解微控制器内部工作原理的工程师，也适合对底层硬件编程感兴趣的学者和学生。 ARM Cortex-M3是一款高效能、低功耗的微处理器核心，广泛应用于物联网(IoT)设备、汽车电子、医疗设备和消费电子产品等众多领域。汇编语言作为与硬件最接近的编程语言，允许程序员直接控制硬件资源，实现高效且精确的代码执行。通过学习ARM Cortex-M3的汇编语言，开发者能够更有效地利用处理器的特性，优化程序性能，特别是对于时间和空间效率要求极高的场合。本书可能包含以下章节和知识点： 1. **汇编语言基础**：介绍汇编语言的基本语法，包括指令集、操作码、寄存器、寻址模式等。 2. **Cortex-M3架构**：详细讲解Cortex-M3处理器的体系结构，如中断处理、内存模型、处理器模式以及异常处理。 3. **编程模型**：讨论Cortex-M3的编程模型，包括堆栈操作、分支指令、中断服务例程(ISR)的设计等。 4. **数据处理指令**：涵盖加法、减法、乘法、位操作等基本数据处理指令的使用。 5. **控制流指令**：介绍跳转、循环和条件执行等控制流指令的实现。 6. **内存访问**：讲解如何通过汇编访问和操作内存，包括直接寻址和间接寻址。 7. **中断和异常**：解释Cortex-M3中的中断和异常处理机制，以及如何在汇编中编写中断服务程序。 8. **调试和分析**：介绍如何使用汇编级调试工具对程序进行调试和性能分析。 9. **汇编与高级语言的交互**：讨论如何在C或C++等高级语言中嵌入汇编代码，实现性能关键部分的优化。通过学习这本书，读者将能够熟练地编写针对Cortex-M3的汇编程序，理解底层硬件的工作方式，从而更好地设计和优化嵌入式系统的软件。无论是对硬件开发者还是软件工程师来说，掌握汇编语言都是提升专业技能的重要一步。

4 Assembly Language Programming

logical unit for the proper execution of different instructions. The functioning of this

block will be explained in detail in Chapter 2. It is necessary to understand its

mechanism in order to write programs in assembly language.

– Nested Vector Interrupt Controller (NVIC): Cortex-M3 is intended to be

embedded in a μcontroller, which includes peripheral units to allow interfacing with

the outside world. These units can be seen as independent micromachines. The

exchanges between them and Cortex-M3 must consequently be rhythmic and

organized so that the sequence of tasks complies with rules (the concept of

priorities) and determinism set in advance by the programmer. NVIC plays the role

of “director”. It is in charge of receiving, sorting and distributing the different

interrupt requests generated by the collection of μcontroller units. It also manages

events that threaten the smooth running of the code being executed (reset, memory

bus problem, division by 0, etc.).

Figure 1.1. Cortex-M3 functional diagram

– Memory Protection Unit (MPU): This block is optional – a designer using

Cortex-M3 to make their μcontroller can choose not to implement this function. This

block allows the allocation of specific read and/or write privileges to specific

memory zones. In this way, when different independent software tasks are executed

in parallel (or more precisely in sharing the common resources of the processor), it

is possible to allocate a memory zone to each task that is inaccessible to the other

tasks. This mechanism therefore allows programmer to secure memory access. It

Overview of Cortex-M3 Architecture 5

usually goes hand-in-hand with the use of an operating system (real-time or

otherwise) for the software layer.

– Bus matrix: This unit is a kind of gigantic intelligent multiplex. It allows

connections to the external buses:

- the ICode bus (32-bit AHB-Lite type

) that carries the memory mappings

allocated to the code and instructions;

- the DCode bus (also 32-bit AHB-Lite type) that is responsible for

reading/writing in data memory zones;

- the System bus (again 32-bit AHB-Lite type), which deals with all system

space access;

- the Private Peripheral Bus (PPB): all peripherals contained in the μcontroller

are added to the Cortex-M3 architecture by the designer. ARM designed a specific

bus to allow exchanges with peripherals. This bus contains 32 bits, but in this case it

is the Advanced Peripheral Bus (APB) type. This corresponds to another bus

protocol (which you may know is less efficient than AHB type, but it is more than

sufficient for access to peripheral units). It should be noted that the bus matrix plays

an important role in transmitting useful information to development units, which are

mentioned in the next section.

1.2.1.2. Development units

The development of programs is an important and particularly time-consuming

step in the development cycle of an embedded application. What is more, if the

project has certification imperatives, it is necessary that tools (software and/or

material) allowing maximum monitoring of the events occurring in each clock cycle

are at its disposition. In Cortex-M3, the different units briefly introduced below

correspond to these monitoring functions. They are directly implanted in the silicon

of the circuit, which allows them to use these development tools at a material level.

An external software layer is necessary, however, to recover and process the

information issued by these units. The generic idea behind the introduction of

hardware solutions is to offer the programmer the ability to test and improve the

reliability of (or certify) his or her code without making any changes. It is

convenient (and usual) to insert some print (“Hello I was here”) into a software

structure to check that the execution passes through this structure. This done, a code

modification is introduced, which can modify the global behavior of the program.

This is particularly true when time management is critical for the system, which, for

2 Advanced High-performance Bus (AHB) is a microcontroller bus protocol brought in by

ARM.

6 Assembly Language Programming

embedded systems controlled by a μcontroller, is almost always the case. The units

relating to monitoring functions in Cortex-M3 include:

– Flash Patch and Breakpoint (FPB): the FPB is the most basic function for this

process. It is linked to the concept of a stopping point (breakpoint), which imposes a

stop on a line of code (that is to say, an instruction in the case of assembly language)

located beforehand. This unit is used to mark instructions so that when they come

into effect, the processor puts itself into a particular mode of operation: debug mode.

Development software (and other pieces of software that use it) can therefore

observe the state of the processor and directly influence the running of the program

in progress.

– Data Watchpoint and Trace (DWT): the concept of a “point of observation” is

the counterpart to the concept of a stopping point for the data. The DWT stops the

program running when it works on marked data rather than a marked instruction.

This action can be in reading, writing, passing on values, etc. The unit can also send

requests to the ITM and ETM units.

– Embedded Trace Macrocell (ETM): the concept of trace includes the capacity

for the hardware to record a sequence of events during program execution. The

recovery of these recordings allows the programmer to analyze the running of the

program, whether good or bad. In the case of ETM, only information on instructions

is stored in a first in, first out (FIFO)-type structure. As with the MPU unit, this unit

is optional.

– Instrumentation Trace Macrocell (ITM): this unit also allows the collection of

trace information on applications (software, hardware or time). The information is

more limited than with the ETM unit but is nevertheless very useful in isolating a

vicious bug. This is especially true if the optional ETM is not present.

– Advanced High-performance Bus Access Port (AHB-AP): this is an

(Input/Output) port within Cortex-M3 that is designed to debug. It allows access to

all records and all addressable memory space. It has priority in the arbitration

policies of the bus matrix. This unit is connected upstream by the Serial Wire JTAG

(Joint Test Action Group) port (SW/JTAG), which is the interface (with its physical

layers) that connects to the outside world, equipped with its part of the JTAG probe.

The JTAG protocol is a standardized protocol used by almost all semiconductor

manufacturers.

– Trace Port Interface Unit (TPUI): the TPUI plays the same role in trace

functions as the SW/JTAG plays in debug functions. Its existence is principally

linked to the fact that it is necessary to sort the external world recordings collected

by the ITM. There is an additional challenge, however, when an ETM unit is

present, as it must also manage the data stored there. Its secondary role is

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