深入理解ARM Cortex-M3汇编编程：Mahout的2012年指南

需积分: 10 49 浏览量更新于2024-07-24 收藏 4.06MB PDF 举报

《Assembly Language Programming: ARM Cortex-M3》是由Vincent Mahout所著，于2012年首次在英国和美国由ISTE Ltd和John Wiley & Sons, Inc.出版的一本专业书籍。该书专注于介绍针对ARM Cortex-M3架构的汇编语言编程。ARM Cortex-M3是一款广泛应用在嵌入式系统中的微处理器，以其低功耗、高效能和高度灵活性而受到开发者的青睐。本书共258页，以PDF格式提供，文件大小为4.06 MB，涵盖了Cortex-M3处理器的底层工作原理、汇编指令集以及如何利用这些指令进行高效的程序设计。作者深入浅出地讲解了汇编语言的基础概念，包括指令体系结构、内存管理、中断处理、数据类型和运算等，旨在帮助读者掌握在Cortex-M3平台上进行实际项目开发所需的技能。版权方面，根据1988年的《版权、设计和专利法》，除非出于研究、个人学习目的或批评与评论，未经出版商书面许可，不得以任何形式复制、存储或传输此书内容。若需进行复制或重印，应遵循CLAA（Copyright Licensing Agency）的相关条款和许可。对于超出这些范围的复制请求，应直接联系ISTE Ltd或John Wiley & Sons, Inc.获取授权，地址分别位于伦敦和新泽西州。书中，Vincent Mahout作为作者，依据版权法律维护了自己的权益，并明确表示了他的身份。该书不仅适合对嵌入式系统有深厚兴趣的专业人士，也适合那些希望深入理解ARM Cortex-M3硬件特性和汇编语言编程初学者作为参考教材。《Assembly Language Programming: ARM Cortex-M3》是一本实用的指南，它提供了从基础到进阶的Cortex-M3汇编语言编程教程，有助于开发者提升对微控制器操作的理解和实践能力。无论是硬件开发者还是软件工程师，都能从中受益匪浅。

4 Assembly Language Programming

logical unit for the proper execution of different instructions. The functioning of this

block will be explained in detail in Chapter 2. It is necessary to understand its

mechanism in order to write programs in assembly language.

– Nested Vector Interrupt Controller (NVIC): Cortex-M3 is intended to be

embedded in a μcontroller, which includes peripheral units to allow interfacing with

the outside world. These units can be seen as independent micromachines. The

exchanges between them and Cortex-M3 must consequently be rhythmic and

organized so that the sequence of tasks complies with rules (the concept of

priorities) and determinism set in advance by the programmer. NVIC plays the role

of “director”. It is in charge of receiving, sorting and distributing the different

interrupt requests generated by the collection of μcontroller units. It also manages

events that threaten the smooth running of the code being executed (reset, memory

bus problem, division by 0, etc.).

Figure 1.1. Cortex-M3 functional diagram

– Memory Protection Unit (MPU): This block is optional – a designer using

Cortex-M3 to make their μcontroller can choose not to implement this function. This

block allows the allocation of specific read and/or write privileges to specific

memory zones. In this way, when different independent software tasks are executed

in parallel (or more precisely in sharing the common resources of the processor), it

is possible to allocate a memory zone to each task that is inaccessible to the other

tasks. This mechanism therefore allows programmer to secure memory access. It

Overview of Cortex-M3 Architecture 5

usually goes hand-in-hand with the use of an operating system (real-time or

otherwise) for the software layer.

– Bus matrix: This unit is a kind of gigantic intelligent multiplex. It allows

connections to the external buses:

- the ICode bus (32-bit AHB-Lite type

) that carries the memory mappings

allocated to the code and instructions;

- the DCode bus (also 32-bit AHB-Lite type) that is responsible for

reading/writing in data memory zones;

- the System bus (again 32-bit AHB-Lite type), which deals with all system

space access;

- the Private Peripheral Bus (PPB): all peripherals contained in the μcontroller

are added to the Cortex-M3 architecture by the designer. ARM designed a specific

bus to allow exchanges with peripherals. This bus contains 32 bits, but in this case it

is the Advanced Peripheral Bus (APB) type. This corresponds to another bus

protocol (which you may know is less efficient than AHB type, but it is more than

sufficient for access to peripheral units). It should be noted that the bus matrix plays

an important role in transmitting useful information to development units, which are

mentioned in the next section.

1.2.1.2. Development units

The development of programs is an important and particularly time-consuming

step in the development cycle of an embedded application. What is more, if the

project has certification imperatives, it is necessary that tools (software and/or

material) allowing maximum monitoring of the events occurring in each clock cycle

are at its disposition. In Cortex-M3, the different units briefly introduced below

correspond to these monitoring functions. They are directly implanted in the silicon

of the circuit, which allows them to use these development tools at a material level.

An external software layer is necessary, however, to recover and process the

information issued by these units. The generic idea behind the introduction of

hardware solutions is to offer the programmer the ability to test and improve the

reliability of (or certify) his or her code without making any changes. It is

convenient (and usual) to insert some print (“Hello I was here”) into a software

structure to check that the execution passes through this structure. This done, a code

modification is introduced, which can modify the global behavior of the program.

This is particularly true when time management is critical for the system, which, for

2 Advanced High-performance Bus (AHB) is a microcontroller bus protocol brought in by

ARM.

6 Assembly Language Programming

embedded systems controlled by a μcontroller, is almost always the case. The units

relating to monitoring functions in Cortex-M3 include:

– Flash Patch and Breakpoint (FPB): the FPB is the most basic function for this

process. It is linked to the concept of a stopping point (breakpoint), which imposes a

stop on a line of code (that is to say, an instruction in the case of assembly language)

located beforehand. This unit is used to mark instructions so that when they come

into effect, the processor puts itself into a particular mode of operation: debug mode.

Development software (and other pieces of software that use it) can therefore

observe the state of the processor and directly influence the running of the program

in progress.

– Data Watchpoint and Trace (DWT): the concept of a “point of observation” is

the counterpart to the concept of a stopping point for the data. The DWT stops the

program running when it works on marked data rather than a marked instruction.

This action can be in reading, writing, passing on values, etc. The unit can also send

requests to the ITM and ETM units.

– Embedded Trace Macrocell (ETM): the concept of trace includes the capacity

for the hardware to record a sequence of events during program execution. The

recovery of these recordings allows the programmer to analyze the running of the

program, whether good or bad. In the case of ETM, only information on instructions

is stored in a first in, first out (FIFO)-type structure. As with the MPU unit, this unit

is optional.

– Instrumentation Trace Macrocell (ITM): this unit also allows the collection of

trace information on applications (software, hardware or time). The information is

more limited than with the ETM unit but is nevertheless very useful in isolating a

vicious bug. This is especially true if the optional ETM is not present.

– Advanced High-performance Bus Access Port (AHB-AP): this is an

(Input/Output) port within Cortex-M3 that is designed to debug. It allows access to

all records and all addressable memory space. It has priority in the arbitration

policies of the bus matrix. This unit is connected upstream by the Serial Wire JTAG

(Joint Test Action Group) port (SW/JTAG), which is the interface (with its physical

layers) that connects to the outside world, equipped with its part of the JTAG probe.

The JTAG protocol is a standardized protocol used by almost all semiconductor

manufacturers.

– Trace Port Interface Unit (TPUI): the TPUI plays the same role in trace

functions as the SW/JTAG plays in debug functions. Its existence is principally

linked to the fact that it is necessary to sort the external world recordings collected

by the ITM. There is an additional challenge, however, when an ETM unit is

present, as it must also manage the data stored there. Its secondary role is

剩余257页未读，继续阅读

b7r34dshi8

粉丝: 0
资源: 5

深入理解ARM Cortex-M3汇编编程：Mahout的2012年指南

深入浅出ARM Cortex-M3汇编语言编程

ARM Cortex-M3 权威指南：菜鸟基础篇

ARM Cortex-M0平台上的Apple II模拟器技术实现

assembly-cortex-m3:cortex-m3 LPC1769（LPCXpresso）和STM32F103（HY-STM32板）的代码（主要是汇编）

从零开始：ARM Cortex-M0+处理器的启动流程详解

CIS---11-Assembly-Programming:CIS-11-34595汇编程序设计课程材料，Sprint 2018

starter-arm-cortex-m0-asm-asst-part-1:为ARM Cortex-M0编译为汇编的简单C程序，用于跟踪执行

ARM Cortex-M3 Keil5 汇编实现 LED

keil uVision4 for ARM Cortex-M3 使用汇编示例

Applerm-II:在 ARM Cortex-M0 上运行的 Apple II 模拟器

最新资源