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"瑞萨RX72T用户手册:硬件使用指南"
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瑞萨RX72T用户手册是一份详细介绍瑞萨RX72T系列32位微控制器的硬件特性和使用方法的手册。该手册是为了帮助用户更好地了解和使用RX72T系列微控制器而编写的。
手册的内容主要分为以下几个部分:绪论、产品概述、硬件特性、引脚说明、电气特性、封装尺寸和引脚间距、引脚排列图、主要功能模块、时钟和复位、存储器、外设接口、ADC、数据通信接口、中断控制器、低功耗模式、调试功能、注意事项和附录等。
首先,在绪论部分,手册介绍了该手册的目的和组织结构,使用户对手册的整体框架有个初步了解,并指导用户如何正确地使用该手册。
其次,在产品概述部分,手册对RX72T系列微控制器进行了总体介绍,包括产品特点、主要应用领域和支持的开发环境等,让用户对该系列微控制器有一个整体的了解。
然后,在硬件特性部分,手册详细介绍了RX72T系列微控制器的硬件特性,包括处理器核心、总线、时钟、复位、存储器、电源管理、中断和外设等,让用户对该系列微控制器的具体硬件特性有一个全面的认识。
接着,在引脚说明部分,手册详细罗列了RX72T系列微控制器的所有引脚,并对每个引脚的功能进行了详细的描述,包括输入输出类型、电气特性等,帮助用户正确选择和使用引脚。
然后,在电气特性部分,手册介绍了RX72T系列微控制器的电气特性,包括电源电压、电流、温度等的要求和限制,以及IO电气特性等,让用户在使用微控制器时能够准确地遵循相关的电气规范。
在封装尺寸和引脚间距部分,手册提供了RX72T系列微控制器所支持的不同封装形式的尺寸和引脚间距的详细信息,方便用户在选择封装时进行参考。
接下来,在引脚排列图部分,手册提供了RX72T系列微控制器的引脚排列图,以帮助用户更清晰地了解每个引脚的位置和功能。
然后,在主要功能模块部分,手册详细介绍了RX72T系列微控制器的主要功能模块,包括处理器核心、存储器、时钟、复位、外设接口等,让用户更深入地了解微控制器的功能。
在时钟和复位部分,手册提供了关于时钟和复位的详细信息,包括时钟源、时钟分频器、复位电路等的设置和使用方法,帮助用户正确地配置和使用这些功能。
接着,在存储器部分,手册介绍了RX72T系列微控制器的存储器的种类和特性,包括闪存、RAM等,使用户能够正确地选择和使用存储器。
然后,在外设接口部分,手册详细介绍了RX72T系列微控制器支持的各种外设接口,包括GPIO、UART、I2C、SPI等,方便用户在实际应用中进行接口的配置和使用。
接下来,在ADC部分,手册详细介绍了RX72T系列微控制器支持的模数转换器(ADC)的特性和使用方法,帮助用户在需要模拟输入的应用中正确地使用ADC。
然后,在数据通信接口部分,手册介绍了RX72T系列微控制器支持的各种数据通信接口,包括CAN、LIN、USB等,使用户能够正确配置和使用这些通信接口。
在中断控制器部分,手册介绍了RX72T系列微控制器的中断控制器的特性和使用方法,方便用户在实际应用中正确配置和使用中断。
接着,在低功耗模式部分,手册详细介绍了RX72T系列微控制器的低功耗模式的种类和特性,帮助用户在需要降低功耗的应用中正确地配置和使用低功耗模式。
然后,在调试功能部分,手册介绍了RX72T系列微控制器支持的调试功能,包括调试接口、调试模式等的使用方法,方便用户进行调试和测试。
最后,在注意事项和附录部分,手册列出了一些在使用RX72T系列微控制器时需要注意的问题和额外的参考资料,帮助用户更好地理解和使用手册。
综上所述,瑞萨RX72T用户手册通过详细介绍RX72T系列微控制器的硬件特性和使用方法,为用户提供了全面的使用指南。该手册的编写和发布,使得用户能够更好地了解和使用RX72T系列微控制器,提高其在实际应用中的开发效率和产品质量。
15.3.7 Bus Error Status Clear Register (BERCLR) ............................................................................. 427
15.3.8 Bus Error Monitoring Enable Register (BEREN) .................................................................... 427
15.3.9 Bus Error Status Register 1 (BERSR1) .................................................................................... 428
15.3.10 Bus Error Status Register 2 (BERSR2) .................................................................................... 428
15.3.11 Bus Priority Control Register (BUSPRI) .................................................................................. 429
15.4 Endian and Data Alignment .............................................................................................................. 431
15.4.1 Data Alignment Control for CS Area ....................................................................................... 431
15.5 Operation of CS Area Controller ....................................................................................................... 436
15.5.1 Separate Bus ............................................................................................................................. 436
15.5.2 Address/Data Multiplexed Bus ................................................................................................. 449
15.5.3 External Wait Function ............................................................................................................. 452
15.5.4 Insertion of Recovery Cycles ................................................................................................... 454
15.5.5 No Access State ........................................................................................................................ 457
15.5.6 Write Buffer Function (External Bus) ...................................................................................... 458
15.5.7 Limitations ................................................................................................................................ 458
15.6 Bus Error Monitoring Section ........................................................................................................... 460
15.6.1 Types of Bus Error ................................................................................................................... 460
15.6.1.1 Illegal Address Access .................................................................................................... 460
15.6.1.2 Timeout ............................................................................................................................ 460
15.6.2 Operations When a Bus Error Occurs ...................................................................................... 460
15.6.3 Conditions Leading to Bus Errors ............................................................................................ 461
15.7 Interrupt ............................................................................................................................................. 461
15.7.1 Interrupt Source ........................................................................................................................ 461
16. Memory-Protection Unit (MPU) .................................................................................................... 462
16.1 Overview ........................................................................................................................................... 462
16.1.1 Types of Access Control ........................................................................................................... 464
16.1.2 Regions for Access Control ...................................................................................................... 464
16.1.3 Background Region .................................................................................................................. 464
16.1.4 Overlap between Regions ......................................................................................................... 464
16.1.5 Instructions and Data that Span Regions .................................................................................. 464
16.2 Register Descriptions ....................................................................................................
..................... 465
16
.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) ............................................. 465
16.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) .............................................. 466
16.2.3 Memory-Protection Enable Register (MPEN) ......................................................................... 467
16.2.4 Background Access Control Register (MPBAC) ..................................................................... 468
16.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) ............................................. 469
16.2.6 Memory-Protection Error Status Register (MPESTS) ............................................................. 470
16.2.7 Data Memory-Protection Error Address Register (MPDEA) ................................................... 471
16.2.8 Region Search Address Register (MPSA) ................................................................................ 472
16.2.9 Region Search Operation Register (MPOPS) ........................................................................... 472
16.2.10 Region Invalidation Operation Register (MPOPI) ................................................................... 473
16.2.11 Instruction-Hit Region Register (MHITI) ................................................................................ 474
16.2.12 Data-Hit Region Register (MHITD) ......................................................................................... 476
16.3 Functions ........................................................................................................................................... 478
16.3.1 Memory Protection ................................................................................................................... 478
16.3.2 Region Search ........................................................................................................................... 478
16.3.3 Protection of Registers Related to the Memory-Protection Unit .............................................. 478
16.3.4 Flow for Determination of Access by the Memory-Protection Function ................................. 479
16.4 Procedures for Using Memory Protection ......................................................................................... 481
16.4.1 Setting Access-Control Information ......................................................................................... 481
16.4.2 Enabling Memory Protection .................................................................................................... 481
16.4.3 Transition to User Mode ........................................................................................................... 481
16.4.4 Processing in Response to Memory-Protection Errors ............................................................. 481
17. DMA Controller (DMACAa) .......................................................................................................... 483
17.1 Overview ........................................................................................................................................... 483
17.2 Register Descriptions ......................................................................................................................... 485
17.2.1 DMA Source Address Register (DMSAR) .............................................................................. 485
17.2.2 DMA Destination Address Register (DMDAR) ...................................................................... 485
17.2.3 DMA Transfer Count Register (DMCRA) ............................................................................... 486
17.2.4 DMA Block Transfer Count Register (DMCRB) ..................................................................... 487
17.2.5 DMA Transfer Mode Register (DMTMD) ............................................................................... 488
17.2.6 DMA Interrupt Setting Register (DMINT) .............................................................................. 489
17.2.7 DMA Address Mode Register (DMAMD) ............................................................................... 491
17.2.8 DMA Offset Register (DMOFR) .............................................................................................. 494
17.2.9 DMA Transfer Enable Register (DMCNT) .............................................................................. 494
17.2.10 DMA Software Start Register (DMREQ) ................................................................................ 495
17.2.11 DMA Status Register (DMSTS) ............................................................................................... 496
17.2.12 DMA Request Source Flag Control Register (DMCSL) .......................................................... 497
17.2.13 DMAC Module Start Register (DMAST) ................................................................................ 498
17.2.14 DMAC74 Interrupt Status Monitor Register (DMIST) ............................................................ 499
17.3 Operation ........................................................................................................................................... 500
17.3.1 Transfer Mode .......................................................................................................................... 500
17.3.2 Extended Repeat Area Function ............................................................................................... 504
17.3.3 Address Update Function using Offset ....................
.................................................................
506
17.3.4 Request Sources ........................................................................................................................ 510
17.3.5 Operation Timing ..................................................................................................................... 511
17.3.6 DMAC Execution Cycles ......................................................................................................... 512
17.3.7 Activating the DMAC .............................................................................................................. 513
17.3.8 Starting DMA Transfer ............................................................................................................. 514
17.3.9 Registers during DMA Transfer ............................................................................................... 514
17.3.10 Channel Priority ........................................................................................................................ 515
17.4 Ending DMA Transfer ....................................................................................................................... 516
17.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations ................... 516
17.4.2 Transfer End by Repeat Size End Interrupt .............................................................................. 516
17.4.3 Transfer End by Interrupt on Extended Repeat Area Overflow ............................................... 516
17.5 Interrupts ............................................................................................................................................ 517
17.6 Event Link ......................................................................................................................................... 519
17.7 Low-Power Consumption Function ................................................................................................... 520
17.8 Usage Notes ....................................................................................................................................... 521
17.8.1 DMA Transfer to External Devices .......................................................................................... 521
17.8.2 DMA Transfer to Peripheral Modules ...................................................................................... 521
17.8.3 Access to the Registers during DMA Transfer ......................................................................... 521
17.8.4 DMA Transfer to Reserved Areas ............................................................................................ 521
17.8.5 Interrupt Request by the DMA Request Source Flag Control Register (DMCSL)
at the End of Each Transfer ...................................................................................................... 521
17.8.6 Setting of DMAC Trigger Select Register of the Interrupt Controller (ICU.DMRSRm) ........ 521
17.8.7 Suspending or Restarting DMA Transfer ................................................................................. 521
18. Data Transfer Controller (DTCa) .................................................................................................. 522
18.1 Overview ........................................................................................................................................... 522
18.2 Register Descriptions ......................................................................................................................... 524
18.2.1 DTC Mode Register A (MRA) ................................................................................................. 524
18.2.2 DTC Mode Register B (MRB) ................................................................................................. 525
18.2.3 DTC Transfer Source Register (SAR) ...................................................................................... 526
18.2.4 DTC Transfer Destination Register (DAR) .............................................................................. 526
18.2.5 DTC Transfer Count Register A (CRA) ................................................................................... 527
18.2.6 DTC Transfer Count Register B (CRB) ................................................................................... 528
18.2.7 DTC Control Register (DTCCR) .............................................................................................. 528
18.2.8 DTC Vector Base Register (DTCVBR) ................................................................................... 529
18.2.9 DTC Address Mode Register (DTCADMOD) ......................................................................... 529
18.2.10 DTC Module Start Register (DTCST) ...................................................................................... 530
18.2.11 DTC Status Register (DTCSTS) ............................................................................................... 531
18.3 Request Sources ................................................................................................................................. 532
18.3.1 Allocating Transfer Information and DTC Vector Table ......................................................... 532
18.4 Operation ....................................................
....................................................................................... 534
18.4.1 Transfer Information Read Skip Function ................................................................................ 536
18.4.2 Transfer Information Write-Back Skip Function ..................................................................... 537
18.4.3 Normal Transfer Mode ............................................................................................................. 538
18.4.4 Repeat Transfer Mode .............................................................................................................. 539
18.4.5 Block Transfer Mode ................................................................................................................ 540
18.4.6 Chain Transfer .......................................................................................................................... 541
18.4.7 Operation Timing ..................................................................................................................... 542
18.4.8 Execution Cycles of the DTC ................................................................................................... 545
18.4.9 DTC Bus Mastership Release Timing ...................................................................................... 545
18.5 DTC Setting Procedure ...................................................................................................................... 546
18.6 Examples of DTC Usage ................................................................................................................... 547
18.6.1 Normal Transfer ....................................................................................................................... 547
18.6.2 Chain Transfer When the Counter is 0 ..................................................................................... 548
18.7 Interrupt Source ................................................................................................................................. 549
18.8 Event Link ......................................................................................................................................... 549
18.9 Low Power Consumption Function ................................................................................................... 550
18.10 Usage Notes ....................................................................................................................................... 551
18.10.1 Start Address of Transfer Information ...................................................................................... 551
18.10.2 Allocating Transfer Information ............................................................................................... 551
18.10.3 Setting the DTC Transfer Request Enable Register in the Interrupt Controller
(ICU.DTCERn) ......................................................................................................................... 552
19. Event Link Controller (ELC) ......................................................................................................... 553
19.1 Overview ........................................................................................................................................... 553
19.2 Register Descriptions ......................................................................................................................... 554
19.2.1 Event Link Control Register (ELCR) ....................................................................................... 554
19.2.2 Event Link Setting Register n (ELSRn)
(n = 0, 3, 4, 7, 10 to 13, 15, 16, 18 to 28, 30, 31, 45 to 58) ...................................................... 555
19.2.3 Event Link Option Setting Register A (ELOPA) ..................................................................... 562
19.2.4 Event Link Option Setting Register B (ELOPB) ...................................................................... 562
19.2.5 Event Link Option Setting Register C (ELOPC) ...................................................................... 563
19.2.6 Event Link Option Setting Register D (ELOPD) ..................................................................... 563
19.2.7 Event Link Option Setting Register E (ELOPE) ...................................................................... 564
19.2.8 Port Group Setting Register n (PGRn) (n = 1, 2) ..................................................................... 565
19.2.9 Port Group Control Register n (PGCn) (n = 1, 2) .................................................................... 566
19.2.10 Port Buffer Register n (PDBFn) (n = 1, 2) ............................................................................... 567
19.2.11 Event Link Port Setting Register m (PELm) (m = 0 to 3) ........................................................ 568
19.2.12 Event Link Software Event Generation Register (ELSEGR) ................................................... 569
19.3 Operation ........................................................................................................................................... 570
19.3.1 Relation between Interrupt Handling and Event Linking ......................................................... 570
19.3.2 Event Linkage ........................................................................................................................... 571
19.3.3 Operation of Peripheral Timer Modules When Event Signal is Input ..................................... 572
19.3.4 Operation of GPTW When Event Signal is Input .................................................................... 572
19.3.5 Operation of A/D and D/A Converters When Event Signal is
Input ........................................ 572
19
.3.6 I/O Port Operation When Event Signal is Input and Event Generation ................................... 573
19.3.7 Example of Procedure for Linking Events ............................................................................... 577
19.4 Usage Notes ....................................................................................................................................... 578
19.4.1 Setting ELSRn Register ............................................................................................................ 578
19.4.2 Setting Bit-Rotating Operation of Output Port Groups ............................................................ 578
19.4.3 Linking DMA/DTC Transfer End Signal as Event .................................................................. 578
19.4.4 Clock Settings ........................................................................................................................... 578
19.4.5 Module Stop Function Setting .................................................................................................. 578
20. I/O Ports ....................................................................................................................................... 579
20.1 Overview ........................................................................................................................................... 579
20.2 I/O Port Configuration ....................................................................................................................... 583
20.3 Register Descriptions ......................................................................................................................... 589
20.3.1 Port Direction Register (PDR) .................................................................................................. 589
20.3.2 Port Output Data Register (PODR) .......................................................................................... 590
20.3.3 Port Input Register (PIDR) ....................................................................................................... 591
20.3.4 Port Mode Register (PMR) ....................................................................................................... 592
20.3.5 Open-Drain Control Register 0 (ODR0) .................................................................................. 593
20.3.6 Open-Drain Control Register 1 (ODR1) .................................................................................. 594
20.3.7 Pull-Up Resistor Control Register (PCR) ................................................................................. 595
20.3.8 Drive Capacity Control Register (DSCR) ................................................................................ 596
20.3.9 Drive Capacity Control Register 2 (DSCR2) ........................................................................... 597
20.4 Usage Notes ....................................................................................................................................... 598
20.4.1 Initialization of the Port Direction Register (PDR) .................................................................. 598
20.4.2 Settings when PH0 and PH4 are to be Used as General Purpose Input Port Pins .................... 601
20.4.3 Handling of Unused Pins .......................................................................................................... 602
21. Multi-Function Pin Controller (MPC) ............................................................................................ 603
21.1 Overview ........................................................................................................................................... 603
21.2 Register Descriptions ......................................................................................................................... 620
21.2.1 Write-Protect Register (PWPR) ................................................................................................ 620
21.2.2 P0n Pin Function Control Register (P0nPFS) (n = 0, 1) .......................................................... 621
21.2.3 P1n Pin Function Control Registers (P1nPFS) (n = 0 to 7) ...................................................... 622
21.2.4 P2n Pin Function Control Registers (P2nPFS) (n = 0 to 7) ...................................................... 624
21.2.5 P3n Pin Function Control Registers (P3nPFS) (n = 0 to 5) ...................................................... 626
21.2.6 P4n Pin Function Control Registers (P4nPFS) (n = 0 to 7) ...................................................... 628
21.2.7 P5n Pin Function Control Registers (P5nPFS) (n = 0 to 5) ...................................................... 629
21.2.8 P6n Pin Function Control Registers (P6nPFS) (n = 0 to 5) ...................................................... 630
21.2.9 P7n Pin Function Control Registers (P7nPFS) (n = 0 to 6) ...................................................... 631
21.2.10 P8n Pin Function Control Registers (P8nPFS) (n = 0 to 2) ...................................................... 632
21.2.11 P9n Pin Function Control Registers (P9nPFS) (n = 0 to 6) ...................................................... 633
21.2.12 PAn Pin Function Control Registers (PAnPFS) (n = 0 to 7) .................................................... 634
21.2.13 PBn Pin Function Control Registers (PBnPFS) (n = 0 to 7)
.................................................... 636
21
.2.14 PCn Pin Function Control Register (PCnPFS) (n = 0 to 6) ...................................................... 637
21.2.15 PDn Pin Function Control Register (PDnPFS) (n = 0 to 7) ..................................................... 638
21.2.16 PEn Pin Function Control Register (PEnPFS) (n = 0 to 6) ...................................................... 639
21.2.17 PFn Pin Function Control Register (PFnPFS) (n = 0 to 3) ....................................................... 641
21.2.18 PGn Pin Function Control Register (PGnPFS) (n = 0 to 2) ..................................................... 642
21.2.19 PHn Pin Function Control Registers (PHnPFS) (n = 0 to 7) .................................................... 643
21.2.20 PKn Pin Function Control Register (PKnPFS) (n = 0 to 2) ..................................................... 644
21.2.21 CS Output Enable Register (PFCSE) ....................................................................................... 645
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