MSP432数字I/O详解：低功耗高性能特性与中断功能

需积分: 35 52 浏览量更新于2024-07-22 收藏 5.68MB PDF 举报

MSP432是一款低功耗与高性能结合的微控制器系列，其数字I/O特性在这款产品中占据核心地位。它提供了独立可编程的I/O接口，支持输入或输出模式的任意组合，并且针对某些端口配置了可编程中断功能，这些中断可以基于输入信号的上升沿或下降沿触发。每个I/O线都有独立的数据寄存器，用于读取和写入数据，以及可配置的上拉或下拉电阻，确保了灵活性和电源管理。特别地，MSP432允许设备在超低功耗模式下通过特定的端口实现唤醒功能，这对于能源效率至关重要。某些I/O端口还具备高驱动能力，这在需要更大电流输出的应用中非常有用。该系列的每个设备可能包含多达11个数字I/O端口，如P1到P10和PJ，其中大部分端口有8条I/O线，但部分端口的I/O数量会有所不同，具体取决于型号规格。 MSP432的I/O操作支持半字宽和字宽访问，例如，P1和P2这样的端口对合在一起形成PA、PB等全宽端口。中断处理采用统一的中断向量（IV）寄存器，应用程序可以通过这些寄存器识别是由哪个子pin引发的事件，即使对于特定端口的中断和唤醒功能，也需要查阅设备特定的数据表以获取详细信息。在编程模型方面，MSP432采用了Cortex-M4F处理器，具有丰富的系统组件，如嵌入式调试接口，以及清晰的内存模型，包括不同的内存区域、访问顺序和异常处理机制。处理器支持多种模式和特权级别，保证软件执行的有序性和安全性。此外，还包括栈管理、寄存器映射、数据类型定义、内存访问规则、异常处理机制（如中断优先级和中断处理过程）、以及故障处理策略等关键知识点。总结来说，MSP432的数字I/O设计注重灵活性、效率和易用性，适用于各种需要低功耗和高性能控制的应用场景，无论是基本的输入输出操作，还是复杂的中断管理和异常处理，都体现了该系列产品的强大功能和先进特性。

www.ti.com

2-42. IPR12 Register............................................................................................................ 122

2-43. IPR13 Register............................................................................................................ 123

2-44. IPR14 Register............................................................................................................ 124

2-45. IPR15 Register............................................................................................................ 125

2-46. STIR Register ............................................................................................................. 126

2-47. STCSR Register .......................................................................................................... 128

2-48. STRVR Register .......................................................................................................... 129

2-49. STCVR Register .......................................................................................................... 130

2-50. STCR Register ............................................................................................................ 131

2-51. CPUID Register ........................................................................................................... 133

2-52. ICSR Register ............................................................................................................. 134

2-53. VTOR Register............................................................................................................ 136

2-54. AIRCR Register ........................................................................................................... 137

2-55. SCR Register.............................................................................................................. 139

2-56. CCR Register.............................................................................................................. 140

2-57. SHPR1 Register .......................................................................................................... 141

2-58. SHPR2 Register .......................................................................................................... 142

2-59. SHPR3 Register .......................................................................................................... 143

2-60. SHCSR Register .......................................................................................................... 144

2-61. CFSR Register ............................................................................................................ 146

2-62. HFSR Register ............................................................................................................ 148

2-63. DFSR Register ............................................................................................................ 149

2-64. MMFAR Register.......................................................................................................... 150

2-65. BFAR Register ............................................................................................................ 151

2-66. AFSR Register ............................................................................................................ 152

2-67. PFR0 Register............................................................................................................. 153

2-68. PFR1 Register............................................................................................................. 154

2-69. DFR0 Register ............................................................................................................ 155

2-70. AFR0 Register............................................................................................................. 156

2-71. MMFR0 Register.......................................................................................................... 157

2-72. MMFR1 Register.......................................................................................................... 158

2-73. MMFR2 Register.......................................................................................................... 159

2-74. MMFR3 Register.......................................................................................................... 160

2-75. ISAR0 Register............................................................................................................ 161

2-76. ISAR1 Register............................................................................................................ 162

2-77. ISAR2 Register............................................................................................................ 163

2-78. ISAR3 Register............................................................................................................ 164

2-79. ISAR4 Register............................................................................................................ 165

2-80. CPACR Register .......................................................................................................... 166

2-81. ICTR Register ............................................................................................................. 168

2-82. ACTLR Register........................................................................................................... 169

2-83. DHCSR Register.......................................................................................................... 171

2-84. DCRSR Register.......................................................................................................... 173

2-85. DCRDR Register.......................................................................................................... 174

2-86. DEMCR Register.......................................................................................................... 175

2-87. FP_CTRL Register ....................................................................................................... 178

2-88. FP_REMAP Register..................................................................................................... 179

2-89. FP_COMP0 Register..................................................................................................... 180

2-90. FP_COMP1 Register..................................................................................................... 181

List of Figures SLAU356–March 2015

Submit Documentation Feedback

www.ti.com

2-91. FP_COMP2 Register..................................................................................................... 182

2-92. FP_COMP3 Register..................................................................................................... 183

2-93. FP_COMP4 Register..................................................................................................... 184

2-94. FP_COMP5 Register..................................................................................................... 185

2-95. FP_COMP6 Register..................................................................................................... 186

2-96. FP_COMP7 Register..................................................................................................... 187

2-97. CTRL Register ............................................................................................................ 189

2-98. CYCCNT Register ........................................................................................................ 191

2-99. CPICNT Register ......................................................................................................... 192

2-100. EXCCNT Register ........................................................................................................ 193

2-101. SLEEPCNT Register ..................................................................................................... 194

2-102. LSUCNT Register......................................................................................................... 195

2-103. FOLDCNT Register....................................................................................................... 196

2-104. PCSR Register............................................................................................................ 197

2-105. COMP0 Register.......................................................................................................... 198

2-106. MASK0 Register .......................................................................................................... 199

2-107. FUNCTION0 Register .................................................................................................... 200

2-108. COMP1 Register.......................................................................................................... 202

2-109. MASK1 Register .......................................................................................................... 203

2-110. FUNCTION1 Register .................................................................................................... 204

2-111. COMP2 Register.......................................................................................................... 206

2-112. MASK2 Register .......................................................................................................... 207

2-113. FUNCTION2 Register .................................................................................................... 208

2-114. COMP3 Register.......................................................................................................... 210

2-115. MASK3 Register .......................................................................................................... 211

2-116. FUNCTION3 Register .................................................................................................... 212

2-117. STIM0 Register ........................................................................................................... 215

2-118. STIM1 Register ........................................................................................................... 215

2-119. STIM2 Register ........................................................................................................... 216

2-120. STIM3 Register ........................................................................................................... 216

2-121. STIM4 Register ........................................................................................................... 217

2-122. STIM5 Register ........................................................................................................... 217

2-123. STIM6 Register ........................................................................................................... 218

2-124. STIM7 Register ........................................................................................................... 218

2-125. STIM8 Register ........................................................................................................... 219

2-126. STIM9 Register ........................................................................................................... 219

2-127. STIM10 Register .......................................................................................................... 220

2-128. STIM11 Register .......................................................................................................... 220

2-129. STIM12 Register .......................................................................................................... 221

2-130. STIM13 Register .......................................................................................................... 221

2-131. STIM14 Register .......................................................................................................... 222

2-132. STIM15 Register .......................................................................................................... 222

2-133. STIM16 Register .......................................................................................................... 223

2-134. STIM17 Register .......................................................................................................... 223

2-135. STIM18 Register .......................................................................................................... 224

2-136. STIM19 Register .......................................................................................................... 224

2-137. STIM20 Register .......................................................................................................... 225

2-138. STIM21 Register .......................................................................................................... 225

2-139. STIM22 Register .......................................................................................................... 226

SLAU356–March 2015 List of Figures

Submit Documentation Feedback

www.ti.com

2-140. STIM23 Register .......................................................................................................... 226

2-141. STIM24 Register .......................................................................................................... 227

2-142. STIM25 Register .......................................................................................................... 227

2-143. STIM26 Register .......................................................................................................... 228

2-144. STIM27 Register .......................................................................................................... 228

2-145. STIM28 Register .......................................................................................................... 229

2-146. STIM29 Register .......................................................................................................... 229

2-147. STIM30 Register .......................................................................................................... 230

2-148. STIM31 Register .......................................................................................................... 230

2-149. TER Register .............................................................................................................. 231

2-150. TPR Register .............................................................................................................. 232

2-151. TCR Register.............................................................................................................. 233

2-152. IWR Register .............................................................................................................. 234

2-153. IMCR Register............................................................................................................. 235

2-154. LAR Register .............................................................................................................. 236

2-155. LSR Register .............................................................................................................. 237

3-1. Reset Classes............................................................................................................. 240

3-2. RSTCTL_RESET_REQ Register ....................................................................................... 244

3-3. RSTCTL_HARDRESET_STAT Register .............................................................................. 245

3-4. RSTCTL_HARDRESET_CLR Register................................................................................ 246

3-5. RSTCTL_HARDRESET_SET Register ................................................................................ 247

3-6. RSTCTL_SOFTRESET_STAT Register............................................................................... 248

3-7. RSTCTL_SOFTRESET_CLR Register ................................................................................ 249

3-8. RSTCTL_SOFTRESET_SET Register ................................................................................ 250

3-9. RSTCTL_PSSRESET_STAT Register................................................................................. 251

3-10. RSTCTL_PSSRESET_CLR Register .................................................................................. 251

3-11. RSTCTL_PCMRESET_STAT Register ................................................................................ 252

3-12. RSTCTL_PCMRESET_CLR Register.................................................................................. 252

3-13. RSTCTL_PINRESET_STAT Register.................................................................................. 253

3-14. RSTCTL_PINRESET_CLR Register ................................................................................... 253

3-15. RSTCTL_REBOOTRESET_STAT Register........................................................................... 254

3-16. RSTCTL_REBOOTRESET_CLR Register ............................................................................ 254

3-17. RSTCTL_CSRESET_STAT Register .................................................................................. 255

3-18. RSTCTL_CSRESET_CLR Register.................................................................................... 255

4-1. IP Protected Secure Zones Representation........................................................................... 260

4-2. Boot Override Flow ....................................................................................................... 261

4-3. Data set-up for Encrypted Update...................................................................................... 268

4-4. Data set-up for IP protected secure zone Unencrypted Update.................................................... 269

4-5. Device Descriptor Table ................................................................................................. 271

4-6. ARM Cortex-M4 Peripheral ID Register Description ................................................................. 272

4-7. Example of ROM PID Entries for MSP432P401xx Device.......................................................... 273

4-8. SYS_REBOOT_CTL Register........................................................................................... 275

4-9. SYS_NMI_CTLSTAT Register .......................................................................................... 276

4-10. SYS_WDTRESET_CTL Register....................................................................................... 277

4-11. SYS_PERIHALT_CTL Register......................................................................................... 278

4-12. SYS_SRAM_SIZE Register ............................................................................................. 279

4-13. SYS_SRAM_BANKEN Register ........................................................................................ 280

4-14. SYS_SRAM_BANKRET Register ...................................................................................... 281

4-15. SYS_FLASH_SIZE Register ............................................................................................ 282

List of Figures SLAU356–March 2015

Submit Documentation Feedback

www.ti.com

4-16. SYS_DIO_GLTFLT_CTL Register...................................................................................... 283

4-17. SYS_SECDATA_UNLOCK.............................................................................................. 284

4-18. SYS_MASTER_UNLOCK Register..................................................................................... 285

4-19. SYS_BOOTOVER_REQ0 Register .................................................................................... 286

4-20. SYS_BOOTOVER_REQ1 Register .................................................................................... 287

4-21. SYS_BOOTOVER_ACK Register ...................................................................................... 288

4-22. SYS_RESET_REQ Register ............................................................................................ 289

4-23. SYS_RESET_STATOVER Register ................................................................................... 290

4-24. SYS_SYSTEM_STAT Register ......................................................................................... 291

5-1. Clock System Block Diagram ........................................................................................... 294

5-2. Module Clock Request System ......................................................................................... 301

5-3. Oscillator Fault Logic ..................................................................................................... 303

5-4. Switch MCLK from DCOCLK to LFXTCLK ............................................................................ 305

5-5. CSKEY Register .......................................................................................................... 307

5-6. CSCTL0 Register ......................................................................................................... 308

5-7. CSCTL1 Register ......................................................................................................... 309

5-8. CSCTL2 Register ......................................................................................................... 311

5-9. CSCTL3 Register ......................................................................................................... 313

5-10. CSCLKEN Register....................................................................................................... 314

5-11. CSSTAT Register......................................................................................................... 315

5-12. CSIE Register ............................................................................................................. 317

5-13. CSIFG Register ........................................................................................................... 318

5-14. CSCLRIFG Register...................................................................................................... 320

5-15. CSSETIFG Register ...................................................................................................... 321

5-16. CSDCOERCAL0 Register ............................................................................................... 322

5-17. CSDCOERCAL1 Register ............................................................................................... 323

6-1. PSS Block Diagram ...................................................................................................... 325

6-2. Supply Voltage Failure and Resulting PSS Action ................................................................... 327

6-3. PSS Action at Device Power-Up........................................................................................ 327

6-4. PSSKEY Register......................................................................................................... 330

6-5. PSSCTL0 Register ....................................................................................................... 331

6-6. PSSIE Register ........................................................................................................... 333

6-7. PSSIFG Register.......................................................................................................... 334

6-8. PSSCLRIFG Register .................................................................................................... 335

7-1. Power Control Manager Interaction .................................................................................... 337

7-2. High Level Power Mode Transitions ................................................................................... 343

7-3. Valid Active Mode Transitions........................................................................................... 344

7-4. Valid LPM0 Transitions .................................................................................................. 344

7-5. Valid LPM3/LPM4 Transitions........................................................................................... 345

7-6. Valid LPM3.5/LPM4.5 Transitions ...................................................................................... 346

7-7. Active mode transition flow. ............................................................................................. 351

7-8. PCMCTL0 Register....................................................................................................... 359

7-9. PCMCTL1 Register....................................................................................................... 361

7-10. PCMIE Register........................................................................................................... 363

7-11. PCMIFG Register ......................................................................................................... 364

7-12. PCMCLRIFG Register.................................................................................................... 365

8-1. Flash Reads, 0 Waitstates............................................................................................... 369

8-2. Flash Reads, 1 Waitstate ................................................................................................ 370

8-3. Immediate/full word program flow ...................................................................................... 377

SLAU356–March 2015 List of Figures

Submit Documentation Feedback

www.ti.com

8-4. Pre-verify error handling for immediate/full word program flow. .................................................... 378

8-5. Post-verify error handling for immediate/full word program flow.................................................... 379

8-6. Burst program flow........................................................................................................ 381

8-7. Handling auto verify error before the burst operation ................................................................ 382

8-8. Handling auto verify error after the burst operation .................................................................. 383

8-9. FLCTL_POWER_STAT Register ....................................................................................... 389

8-10. FLCTL_BANK0_RDCTL Register ...................................................................................... 390

8-11. FLCTL_BANK1_RDCTL Register ...................................................................................... 392

8-12. FLCTL_RDBRST_CTLSTAT Register ................................................................................. 394

8-13. FLCTL_RDBRST_STARTADDR Register............................................................................. 395

8-14. FLCTL_RDBRST_LEN Register........................................................................................ 396

8-15. FLCTL_RDBRST_FAILADDR Register................................................................................ 397

8-16. FLCTL_RDBRST_FAILCNT Register.................................................................................. 398

8-17. FLCTL_PRG_CTLSTAT Register ...................................................................................... 399

8-18. FLCTL_PRGBRST_CTLSTAT Register ............................................................................... 400

8-19. FLCTL_PRGBRST_STARTADDR Register........................................................................... 402

8-20. FLCTL_PRGBRST_DATA0_0 Register ............................................................................... 403

8-21. FLCTL_PRGBRST_DATA0_1 Register ............................................................................... 403

8-22. FLCTL_PRGBRST_DATA0_2 Register ............................................................................... 404

8-23. FLCTL_PRGBRST_DATA0_3 Register ............................................................................... 404

8-24. FLCTL_PRGBRST_DATA1_0 Register ............................................................................... 405

8-25. FLCTL_PRGBRST_DATA1_1 Register ............................................................................... 405

8-26. FLCTL_PRGBRST_DATA1_2 Register ............................................................................... 406

8-27. FLCTL_PRGBRST_DATA1_3 Register ............................................................................... 406

8-28. FLCTL_PRGBRST_DATA2_0 Register ............................................................................... 407

8-29. FLCTL_PRGBRST_DATA2_1 Register ............................................................................... 407

8-30. FLCTL_PRGBRST_DATA2_2 Register ............................................................................... 408

8-31. FLCTL_PRGBRST_DATA2_3 Register ............................................................................... 408

8-32. FLCTL_PRGBRST_DATA3_0 Register ............................................................................... 409

8-33. FLCTL_PRGBRST_DATA3_1 Register ............................................................................... 409

8-34. FLCTL_PRGBRST_DATA3_2 Register ............................................................................... 410

8-35. FLCTL_PRGBRST_DATA3_3 Register ............................................................................... 410

8-36. FLCTL_ERASE_CTLSTAT Register ................................................................................... 411

8-37. FLCTL_ERASE_SECTADDR Register ................................................................................ 412

8-38. FLCTL_BANK0_INFO_WEPROT Register............................................................................ 413

8-39. FLCTL_BANK0_MAIN_WEPROT Register ........................................................................... 414

8-40. FLCTL_BANK1_INFO_WEPROT Register............................................................................ 416

8-41. FLCTL_BANK1_MAIN_WEPROT Register ........................................................................... 417

8-42. FLCTL_BMRK_CTLSTAT Register .................................................................................... 419

8-43. FLCTL_BMRK_IFETCH Register....................................................................................... 420

8-44. FLCTL_BMRK_DREAD Register ....................................................................................... 421

8-45. FLCTL_BMRK_CMP Register .......................................................................................... 422

8-46. FLCTL_IFG Register ..................................................................................................... 423

8-47. FLCTL_IE Register ....................................................................................................... 424

8-48. FLCTL_CLRIFG Register................................................................................................ 425

8-49. FLCTL_SETIFG Register ................................................................................................ 426

8-50. FLCTL_READ_TIMCTL Register ....................................................................................... 427

8-51. FLCTL_READMARGIN_TIMCTL Register ............................................................................ 428

8-52. FLCTL_PRGVER_TIMCTL Register ................................................................................... 429

List of Figures SLAU356–March 2015

Submit Documentation Feedback

剩余810页未读，继续阅读

小小天之水

粉丝: 0
资源: 5

MSP432数字I/O详解：低功耗高性能特性与中断功能

msp432例程及其原理图（例程不能直接在keil打开，需要自己添加工程）.7z

MSP432P401R 数据表 (Rev. H) 中文.zip

【官方英文版文档高质量翻译】MSP432P401数据手册【翻译】【中文版】.pdf

msp432技术手册，keil5，以及两个msp432芯片包，MSP432E4-DFP，MSP432P4xx-DFP

msp432p401r数据手册.pdf

msp430用户手册

MSP430 用户手册

msp432p401r中文数据手册.pdf

msp432p401R固件库及中文手册.zip

MSP432P4011 技术参考手册：Cortex-M4F 处理器详解

最新资源