Freescale i.MX31/MCIMX31L 嵌入式多媒体处理器规格说明书

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"Freescale的MCIMX31是一款基于ARM11内核的多媒体应用处理器，适用于功能丰富的手机、便携式媒体播放器、移动游戏设备、个人数字助手（PDAs）和无线PDA等低功耗高性能设备。" MCIMX31是Freescale Semiconductor推出的一款先进的应用处理器，其核心是ARM11微处理器架构。ARM11系列是ARM公司设计的32位RISC（精简指令集计算）处理器，以其高效能和低功耗特性著称，广泛应用于各种嵌入式系统中。MCIMX31的发布日期为2006年，文档版本为Rev.1.4，这意味着它是一个初期版本，具体规格和信息可能会随时间更新。该处理器提供了多媒体处理能力，特别适合那些需要在有限功耗预算下实现高性能表现的设备。例如，它能够支持功能丰富的手机实现更多的智能功能，如高清通话、多媒体消息服务和互联网浏览；在便携式媒体播放器中，它可以流畅地处理音频和视频播放，同时保持较长的电池寿命；对于移动游戏机器，MCIMX31可以提供足够的处理能力来运行复杂的游戏引擎和图形渲染；在个人数字助手和无线PDA中，它能够支持快速的数据处理和多任务操作。 MCIMX31和MCIMX31L的区别可能在于功耗或温度等级。MCIMX31VKN5和MCIMX31LVKN5是两个不同的封装选项，它们都具有0°C至+70°C的工作温度范围，并采用MAPBGA-457封装。这种封装技术（Multi-Chip Package Ball Grid Array）允许在小型化设备中集成大量引脚，从而提高了电路板空间的利用率。处理器的特性可能包括高速缓存、内存接口、图形处理单元（GPU）、音频和视频编解码器以及多种外设接口，如USB、Ethernet、UART和SPI等。这些接口使得MCIMX31能够与各种外围设备通信，构建完整的系统解决方案。此外，它可能还具备电源管理单元，以优化不同工作模式下的功耗。 MCIMX31是一款为满足现代数字设备需求而设计的高效能、低功耗处理器，其强大的多媒体处理能力和灵活的接口使其成为多种消费电子产品的理想选择。在开发基于MCIMX31的系统时，工程师需要考虑如何利用其硬件加速功能，优化软件栈，以及如何在保持性能的同时最大限度地降低功耗。

i.MX31/i.MX31L Advance Information, Rev. 1.4

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Preliminary

Functional Description and Application Information

2.3.19 PCMCIA Host Adapter (PCMCIA)

The PCMCIA Host Adapter provides the control logic for PCMCIA socket interfaces, and requires some

additional external analog power switching logic and buffering. The PCMCIA host adapter module is fully

compliant with the PCMCIA standard release 2.1 (PC Card -16) and supports one PCMCIA socket. The

adapter supports hot-insertion, card detection and removal, CompactFlash

, and ATA emulation in

TrueIDE mode. The PCMCIA maps to common memory space, attribute memory space and I/O space.

Each space can be up to 64Mbyte in size. As part of the EMI complex the PCMCIA shares its pins with

the WEIM, SDRAMC, and NFC.

2.3.20 Pulse-Width Accelerator (PWM)

The PWM has a 16-bit counter and is optimized to generate sounds from stored sample audio images and

it can also generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound. The following

features characterize the PWM. the 16-bit up-counter has a source selectable clock with 4 x 16 FIFO to

minimize interrupt overhead. Clock in frequency is controlled by a12-bit prescaler for division of clock.

Capable of sound and melody generation the PWM has an active high or active low configurable output

and can be programmed to be active in low power and debug modes. The PWM can be programmed to

generate interrupts at compare and rollover events.

2.3.21 Random Number Generator Accelerator (RNGA)

The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. The

RNGA is designed to comply with FIPS-140 standards for randomness and non-determinism. The random

bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration

of the shift registers ensures statistically good data (that is, data that looks random). The oscillators with

their unknown frequencies provide the required entropy needed to create random data.

It is important to note that there is no known cryptographic proof showing that this is a secure method of

generating random data. In fact, there may be an attack against the random number generator described in

this document if its output is used directly in a cryptographic application (the attack is based on the

linearity of the internal shift registers). Due to lack of a secure method and the potential for attacks,

Freescale Semiconductor recommends that the random data produced by this module be used as an input

seed to a NIST approved (based on DES or SHA-1) or cryptographically secure (RSA Generator or BBS

Generator) random number generation algorithm. It is also recommended that other sources of entropy be

used along with the RNGA to generate the seed to the pseudo-random algorithm. But this is optional. The

more random sources combined to create the seed the better.

The RNGA uses a 32-bit IP Bus slave interface and contains a 16 × 32 FIFO. It provides a Secure mode

or operations as well as a power saving mode

2.3.22 Real Time Clock (RTC)

The RTC module maintains the system clock, provides stopwatch, alarm, and interrupt functions, and

supports the following features.

• Full clock—days, hours, minutes, seconds

Functional Description and Application Information

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Preliminary

• Minute countdown timer with interrupt

• Programmable daily alarm with interrupt

• Sampling timer with interrupt

• Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

• Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal)

The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment

the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC

interrupts when the TOD settings reach programmed values. The sampling timer generates

fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small

boundaries.

2.3.23 Run-TIme Integrity Checker (RTIC)

The RTIC is one of the security components in the i.MX31 and i.MX31L. Its purpose is to ensure the

integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability

to verify the memory contents during system boot and during run-time execution. If the memory contents

at runtime fail to match the hash signature, an error in the security monitor is triggered.

The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite bus

master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory (up

to two segments per block) and works during and with High Assurance Boot (HAB) process. It provides

Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a

programmable DMA bus duty cycle timer and its own watchdog timer.

The RTIC operates in two primary modes: One time hash mode and continuous hash mode.

The One time hash mode is used during HAB for code authentication or one time integrity checking during

which it stores the hash result internally and signals the ARM11 using an interrupt. In Continuous hash

mode the RTIC is used continuously to verify integrity of memory contents by checking re-generated hash

against internally stored values and interrupts host only if error occurs.

2.3.24 Security Controller Module (SCC)

Security and security services, in an embedded or data processing platform, refer to the i.MX31 and

i.MX31L processor’s ability to provide mandatory and optional information protection services.

Information in this context refers to all embedded data, both program store and data load. Therefore, a

secure platform is intended to protect information/data from unauthorized access in the form of inspection

(read), modification (write) or execution (use). Security assurance refers to the degree of confidence that

security claims are actually met and is therefore associated with the resources available to, and the integrity

of, a given security design.

The SCC is a hardware security component composed of two subblocks, the Secure RAM and the Security

Monitor Overall its primary functionality is associated with establishing a centralized security state

controller and hardware security state with a hardware configured, unalterable security policy. It also

provides an uninterruptedly hardware mechanism to detect and respond to threat detection signals

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Preliminary

Functional Description and Application Information

(specifically platform test access signals). It also serves as a device unique data protection/encryption

resource to enable off chip storage of security sensitive data and an internal storage resource which

automatically and irrevocably destroys plain text security sensitive data upon threat detection.

2.3.25 Secure Digital Host Controller (SDHC)

The MultiMediaCard (MMC), is a universal low cost data storage and communication media that is

designed to cover a wide area of applications as electronic toys, organizers, PDAs and smart phones etc.

The MMC communication is based on an advanced 7 pin serial bus designed to operate in a low voltage

range. The Secure Digital Card (SD), is an evolution of MMC technology, with two additional pins in the

form factor. It is specifically designed to meet the security, capacity, performance, and environment

requirement inherent in newly emerging audio and video consumer electronic devices. The physical form

factor, pin assignment and data transfer protocol are forward compatible with the MultiMediaCard with

some additions. Under SD, it can be categorized into Memory and I/O. The memory card invokes a

provide the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low

power consumption for mobile electronic devices.

The SDHC controls the MMC, SD memory, and I/O cards by sending commands to cards and performing

data accesses to/from the cards.The Multimedia Card/Secure Digital Host module (MMC/SD) integrates

both MMC support along with SD memory and I/O functions. The SDHC is fully compatible with the

MMC System Specification Version 3.0 as well as compatible with the SD Memory Card Specification

1.0, and SD I/O Specification 1.0 with 1/4 channel(s). The maximum data rate in 4-bit mode is 100 Mbps.

The SDHC uses a built-in programmable frequency counter for SDHC bus and provides a maskable

hardware interrupt for SDIO Interrupt, Internal status & FIFO status and it has a 32x16-bit data FIFO

buffer built-in.

2.3.26 SDMA

The SDMA architecture offers highly-competitive DMA Controller features combined with

software-based virtual-DMA flexibility. Furthermore, it enables data transfers between peripheral I/O

devices and internal/external memories.

The Smart Direct Memory Access (SDMA) controller is a critical piece of hardware in a highly integrated

IC like a 3G Baseband chip or a Multimedia SoC. It helps maximizing system performance by off-loading

the CPU in dynamic data routing. It contains a custom RISC core along with its RAM, ROM, the three

DMA units, the CRC unit, and the scheduler.

The SDMA is used to execute short routines that perform DMA transfers; these routines or programs are

called scripts hereafter. The Instruction-Set is composed of single cycle instructions with the exception of

Load/Store instructions to the internal memory (RAM, ROM and memory mapped registers), to the

registers of the DMA and CRC units, and Branch instructions that may require several cycles to execute.

The SDMA core is interfaced to its own memory via the SDMA System Bus. The SDMA System Bus

supports a 32-bit data path and a 16-bit address bus. DMA units are interfaced to the CORE via the

Functional Unit Bus and use dedicated registers to perform DMA transfers.

Functional Description and Application Information

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Preliminary

The SDMA memory is constituted of a ROM and a RAM. The ROM contains startup scripts (for example,

boot code) and other common utilities which are referenced by the scripts that reside in the RAM. The

internal RAM is divided into a context area and a script area.

Every transfer channel requires one context area to keep the contents of all the CORE and units registers

while it is inactive. Channel scripts are downloaded into the internal RAM by the SDMA using a dedicated

channel that is started during the boot sequence. Downloads are invoked using command and pointers

provided by the MCU or DSP. Every channel contains a corresponding channel script that is located in

RAM and/or ROM; and it can be reconfigured independently on an “as needed” basis. This permits a wide

range of SDMA functionality while using the lowest internal memory footprint possible. Channel scripts

can be stored in an external, large capacity, FLASH memory and downloaded when needed. The SDMA

can be configured with any mixture of scripts to enable an endless combination of supported services.

The scheduler is responsible for monitoring and detecting DMA requests, mapping them to channels and

mapping individual channels to a pre-configured priority. At any point in time, the scheduler will present

the highest priority channel requiring service to the SDMA core. A special SDMA core instruction is used

to “conditionally yield” the current channel being executed to an eligible channel that requires service. If,

and only if, an eligible channel is pending will the current execution of a channel be pre-empted. There are

two “yield” instructions that differently determine the eligible channels: in the first version, eligible

channels are pending channels with a strictly higher priority than the current channel priority; in the second

version (“yieldage”), eligible channels are pending channels with a priority that is greater or equal to the

current channel priority. The scheduler detects devices needing service through its 32 DMA request inputs.

After a request is detected, the scheduler determines the channel(s) that is (are) triggered by this request

and marks it (them) as pending in the “Channel Pending (EP)” register. The priorities of all the pending

channels are combined and continuously evaluated in order to update the highest pending priority. The

channel pending flag is cleared by the channel script when the transfer has completed.

The MCU Control module contains the control registers which are used to configure the 32 individual

channels. There are 32 Channel Enable Registers: every register is used to map one DMA request to any

desired combination of channels. The 32 Priority Registers are used to assign a programmable 1-of-7 level

priority to every possible channel. This module also contains all other control registers that can be accessed

by the MCU.

The DSP Control module, when available, contains a restricted set of registers that enable the DSP to

control the channels that have been allocated by the MCU approximately the same set of registers as the

MCU Control module. The SDMA is either owned by the MCU or the DSP, never by both at the same time

for security reasons. The master (MCU or DSP) that owns the SDMA is able to allocate channels to the

other master; the latter that is not controlling the SDMA has a limited access to its control registers.

The 32 DMA requests that are connected to the scheduler come from a variety of sources. The “receive

examples of DMA requests that can be connected to the SDMA. These requests can be used to trigger a

specific SDMA channel, or several channels. This feature can be used to realize a “just-in-time” data

exchange between the two processors to relax the requirement to meet critical deadlines.

The embedded nature of the SDMA requires on-chip debug capability to assure product quality and

reliability and to realize the full performance capabilities of the core. The OnCE compatible debug port

i.MX31/i.MX31L Advance Information, Rev. 1.4

20 Freescale Semiconductor

Preliminary

Functional Description and Application Information

includes support for setting breakpoints, Single-Step & Trace and register dump capability. In addition, all

memory locations are accessible from the debug port.

2.3.27 Subscriber Identification Module (SIM)

The SIM Interface Module (SIM) is designed to facilitate communication to SIM cards or Eurochip

pre-paid phone cards. The SIM module has two ports that can be used to interface with the various cards.

The interface with the MCU is via a 16-bit connection, The SIM module I/O interface can be operated in

one of three modes of operation.

Two wire interface. In this mode both the IC pin RX and IC pin TX are used to interface to the smartcard.

This is activated by resetting the 3volt bit in the port control register to a “0”.

External one wire interface. In this mode the IC pins RX and TX are tied together external to the IC and

routed to the smartcard. The 3volt bit in the port control register is reset to a “0” and the OD bit in the

OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin (RX-TX) must be pulled

high by a resistor. The value should be selected small enough to give a fast enough rise time.

Internal one wire interface. In this mode the IC pin TX is routed to the smartcard. The receive pin RX is

connected to the TX pin internal to the IC. The 3volt bit in the port control register is reset to a “1” and the

OD bit in the OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin TX must

be pulled high by a resistor. The value should be selected small enough to give a fast enough rise time.

2.3.28 Secure JTAG Controller (SJC)

The IEEE1149.1 JTAG test access port (TAP) supports IEEE1149.1 v2001 standard features, access to

OnCE and ICE of each Core, debug features to improve controllability and absorbability of the Cores for

debug purposes, manufacturing test features (special test modes, PLL bypass, memory BIST and

Burn-in...). The SJC provides debug and test control with the maximum security and provide a flexible

architecture for future derivatives or future multi-cores architecture (how to add-remove a Core, software

and hardware implications). JTAG pins can be muxed to the PCS bus connectors.

The SJC operates at maximum 1/8 the slowest frequency of the accessed OnCE/ICE. For example in

normal operation (no core in low-power mode), this frequency will be 1/8 of the SDMA frequency if this

core is present in the TDI-TDO chain (serially connected with other cores or standalone). User needs also

to take into account the 25MHz frequency limitation on the CE bus.

In addition, secure JTAG options are provided to protect debug resources from attacks by unauthorized

users. The secure JTAG design prevents the debug architecture from compromising security.

2.3.29 Synchronous Serial Interface (SSI)

The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices.

These serial devices can be standard codecs, Digital Signal Processors (DSPs), microprocessors,

peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and

Intel AC97 standard.

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