93C66数据手册：全面解析5V单电源操作的低功耗存储器

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"93C66是一款由Microchip Technology Inc.生产的4K位低电压串行电可擦除只读存储器（EEPROM），适用于需要低功耗、非易失性存储的应用。该器件有两种组织结构：512x8位（93C66A）和256x16位（93C66B）。其特性包括单电源5.0V操作，低功耗CMOS技术，主动工作电流典型值为1mA，待机电流最大为1µA。" 93C66的主要特点包括： 1. **单电源5.0V操作**：这使得93C66能够在标准的5V系统中运行，简化了电路设计。 2. **低功耗CMOS技术**：采用这种技术，93C66在活动状态下消耗的电流非常低，仅为1mA（典型值），而在待机模式下，最大电流不超过1µA，这极大地延长了电池寿命，尤其适合电池供电或能源受限的设备。 3. **内存组织**：93C66A提供512个8位存储单元，而93C66B则提供256个16位存储单元，两种组织方式满足不同容量的需求。 4. **自定时抹除和写入周期**：包括自动抹除功能，使得在执行抹除和写入操作时，用户无需关心时间控制，提高了使用的便利性。 5. **自动ERAL before WRAL**：在写入操作前自动执行erase操作，确保数据的正确写入，避免了数据损坏。 6. **上电/断电数据保护电路**：保护存储在芯片中的数据不受电源波动的影响，保证数据的安全性。 7. **三线串行接口**：遵循工业标准，提供简单易用的通信方式，减少了外部控制电路的复杂性。 8. **设备状态信号**：在抹除和写入过程中，设备会通过状态信号反馈当前操作的状态，有助于调试和故障排除。 9. **顺序读取功能**：允许连续读取内存中的数据，提高了数据访问效率。 10. **100,000次E/W周期保证**：具有极高的耐用性，能承受大量写入和擦除操作。 11. **数据保留时间超过200年**：即使在断电的情况下，也能长期保存数据，确保了数据的持久性。 12. **封装形式**：提供8引脚PDIP和SOIC封装，适配各种安装需求，且有适用于不同温度范围的版本。这些特性使93C66非常适合应用于汽车电子、嵌入式系统和其他需要可靠非易失性存储的场合。由于其低功耗和小型封装，它也常见于便携式设备和远程传感器等应用中。操作码和时序图是理解和编程93C66的关键，它们定义了如何与设备进行通信以及执行读写操作的具体步骤。不过，这些具体细节没有在提供的摘要信息中给出，通常会在数据手册的详细部分找到。

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1998 Microchip Technology Inc.

Preliminary

DS21207B-page 3

93C66A/B

2.0 PIN DESCRIPTION

2.1 Chip Select (CS)

A high level selects the device; a low level deselects the

device and forces it into standby mode. However, a pro-

gramming cycle which is already in progress will be

completed, regardless of the Chip Select (CS) input

signal. If CS is brought low during a program cycle, the

device will go into standby mode as soon as the pro-

gramming cycle is completed.

CS must be low for 250 ns minimum (T

CSL

) between

consecutive instructions. If CS is low, the internal con-

trol logic is held in a RESET status.

2.2 Serial Clock (CLK)

The Serial Clock (CLK) is used to synchronize the com-

munication between a master device and

the 93C66A/B. Opcodes, addresses, and data bits

are clocked in on the positive edge of CLK. Data bits

are also clocked out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (T

CKH

) and

clock low time (T

CKL

). This gives the controlling master

freedom in preparing opcode, address, and data.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but the START condition has not been

detected, any number of clock cycles can be received

by the device without changing its status (i.e., waiting

for a START condition).

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

After detecting a START condition, the speciﬁed num-

ber of clock cycles (respectively low to high transitions

of CLK) must be provided. These clock cycles are

required to clock in all required opcodes, addresses,

and data bits before an instruction is executed

(Table 2-1 and Table 2-2). CLK and DI then become

don't care inputs waiting for a new START condition to

be detected.

2.3 Data In (DI)

Data In (DI) is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

2.4 Data Out (DO)

Data Out (DO) is used in the READ mode to output

data synchronously with the CLK input (T

after the

positive edge of CLK).

This pin also provides READY/B

USY status informa-

tion during ERASE and WRITE cycles. READY/B

USY

status information is available on the DO pin if CS is

brought high after being low for minimum chip select

low time (T

CSL

) and an ERASE or WRITE operation

has been initiated. The status signal is not available on

DO, if CS is held low during the entire ERASE or

WRITE cycle. In this case, DO is in the HIGH-Z mode.

If status is checked after the ERASE/WRITE cycle, the

data line will be high to indicate the device is ready.

TABLE 2-1: INSTRUCTION SET FOR 93C66A

TABLE 2-2: INSTRUCTION SET FOR 93C66B

Note:

CS must go low between consecutive

instructions.

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE

1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12

ERAL

1 00 10XXXXXXX — (RDY/BSY)12

EWDS

1 00 00XXXXXXX — HIGH-Z 12

EWEN

1 00 11XXXXXXX — HIGH-Z 12

READ

1 10 A8A7A6A5A4A3A2A1A0 — D7 - D0 20

WRITE

1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20

WRAL

1 00 01XXXXXXX D7 - D0 (RDY/BSY)20

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE

1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11

ERAL

1 00 10XXXXXX — (RDY/BSY)11

EWEN

1 00 11XXXXXX — HIGH-Z 11

EWDS

1 00 00XXXXXX — HIGH-Z 11

READ

1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27

WRITE

1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27

WRAL

1 00 01XXXXXXD15 - D0 (RDY/BSY)27

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