TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input data bits
DATA IN is internally connected to a 4-bit serial input data register. The input data selects a different mode or
selects different analog input channels. The host provides the data word with the MSB first. Each data bit clocks
in on the edge (rising or falling depending on the status of INV CLK
and FS) of the I/O CLK sequence. The input
clock can be inverted by grounding INV CLK
(see Table 3 for the list of software programmed operations set
by the input data).
Table 3. TLV1544/1548 Software-Programmed Operation Modes
INPUT DATA BYTE
FUNCTION SELECT
A3 – A0
COMMENT
BINARY HEX
Analog channel A0 for TLV1548 selected 0000b 0h Channel 0 for TLV1544
Analog channel A1 for TLV1548 selected 0001b 1h
Analog channel A2 for TLV1548 selected 0010b 2h Channel 1 for TLV1544
Analog channel A3 for TLV1548 selected 0011b 3h
Analog channel A4 for TLV1548 selected 0100b 4h Channel 2 for TLV1544
Analog channel A5 for TLV1548 selected 0101b 5h
Analog channel A6 for TLV1548 selected 0110b 6h Channel 3 for TLV1544
Analog channel A7 for TLV1548 selected 0111b 7h
Software power down set 1000b 8h No conversion result (cleared by any access)
Fast conversion rate (10 µs) set 1001b 9h No conversion result (cleared by setting to fast)
Slow conversion rate (40 µs) set 1010b Ah No conversion result (cleared by setting to slow)
Self-test voltage (V
ref
)
– V
ref–
)/2 selected 1011b Bh Output result = 200h
Self-test voltage V
ref
*
selected 1100b Ch Output result = 000h
Self-test voltage V
ref
)
selected 1101b Dh Output result = 3FFh
Reserved 1110b Eh No conversion result
Reserved 1111b Fh No conversion result
analog inputs and internal test voltages
The eight analog inputs and the three internal test inputs are selected by the 11-channel multiplexer according
to the input data bit as shown in Table 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
The device can be operated in two distinct sampling modes: normal sampling mode (fixed sampling time) and
extended sampling mode (flexible sampling time). When CSTART
is held high, the device is operated in normal
sampling mode. When operated in normal sampling mode, sampling of the analog input starts on the rising edge
of the fourth I/O CLK pulse in the microprocessor interface mode (and on the fourth falling edge of I/O CLK in
the DSP interface mode). Sampling continues for 6 I/O CLK periods. The sample is held on the falling edge of
the tenth I/O CLK pulse in the microprocessor interface mode. The sample is held on the falling edge of the tenth
I/O CLK pulse in the DSP interface mode.The three test inputs are applied to the multiplexer, then sampled and
converted in the same manner as the external analog inputs.
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