6位250 MS/s低功耗CMOS模数转换器设计

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"这篇论文介绍了一种新型的6位250兆样本/秒(MS/s)模数转换器(ADC)，特别适用于低功耗、低成本的CMOS集成系统。设计采用改进的逐次逼近ADC架构，结合混合模式减法器，以减少整体功率消耗和系统复杂性。实验证明，该ADC在3.3V电压下工作时，功率消耗低于30毫瓦，最高采样速率达到250 MS/s。通过微调，工作电压可降至0.8V。此ADC在TSMC 0.35微米单多层金属(SPQM)CMOS工艺下仅占用0.1平方毫米的面积，适合于标准CMOS技术中的低功耗、低成本VLSI实现，尤其适用于系统级芯片(SoC)设计。" 本文重点讨论了ADC（模数转换器）的低功耗设计策略。传统的逐次逼近ADC在高速和低功耗需求之间往往难以平衡，而本文提出的新架构解决了这一问题。混合模式减法器是该设计的关键创新点，它能有效降低ADC内部的功率消耗，同时保持高速运行的能力。ADC的功耗与速度性能之间的优化对于便携式电子设备和无线通信系统至关重要，因为这些应用通常对电源效率有严格要求。实验结果显示，该6位ADC能在3.3V电源电压下以250 MS/s的速度运行，这在同类ADC中表现出色。更重要的是，通过设计调整，ADC的运行电压可以进一步降低到0.8V，这不仅有助于节省能源，还能延长设备的电池寿命。此外，ADC的小型化设计（0.1mm²）意味着它可以在有限的空间内集成到复杂的SoC设计中，这对于现代微电子设备的尺寸和集成度要求具有重要意义。关键词包括：ADC、低电压、类似并行操作、逐次逼近。这些关键词反映了论文的主要研究领域和技术特点。文章的第一部分，即引言，通常会概述高精度CMOS ADC在现代电子系统中的重要性，特别是对于那些需要高效能、低功耗解决方案的场合，如无线通信、医疗成像和信号处理等领域。这篇论文提出了一种创新的6位250 MS/s ADC设计，它以低功耗、小体积和高性能为目标，适应了当前微电子技术的发展趋势，对于推动低功耗CMOS集成系统和SoC设计的进步具有显著价值。

54 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

A New Successive Approximation Architecture for

Low-Power Low-Cost CMOS A/D Converter

Chi-Sheng Lin and Bin-Da Liu, Senior Member, IEEE

Abstract—A new 6-bit 250 MS/s analog-to-digital converter

(ADC) is proposed for low-power low-cost CMOS integrated

systems. This design is based on an improved successive ap-

proximation ADC with a mixed-mode subtracter that minimizes

the overall power consumption and system complexity. The

experimental results indicate that this ADC works up to 250 MS/s

with power consumption less than 30 mW at 3.3 V. Moreover, the

operating voltage is scaled down to 0.8 V using a slight adjustment.

The ADC occupies only 0.1 mm

with the TSMC 0.35- m single

ploy quadruple metal (SPQM) CMOS technology. This design is

suitable for standard CMOS technology with low-power low-cost

VLSI implementation. It is well applied when embedded into

system-on-chip (SoC) circuit designs.

Index Terms—ADC, low voltage, parallel-like, successive

approximation.

I. INTRODUCTION

IGH performance CMOS analog-to-digital converters

(ADCs) are key components in mixed-signal integrated

circuits. Recent ADC applications are used increasingly in

digital data reading fields, such as hard disk drives, digital

videodiscs and local-area networks [1], [2]. High sampling

speed is required in all of these applications, resolution as low

as 6-bit, however, is sufficient.

Among these low-resolution high-speed CMOS ADC design

techniques, the flash architecture is one of the best solutions

for high-speed low-latency operations [3]. However, with the

number of bits

, the flash architecture requires com-

parators and the power, area and input capacitance are propor-

tional to

. Folding CMOS ADC is another good architec-

ture for high-speed operations and simple hardware design. This

is a technique for reducing the number of comparators used in

the flash architecture [4]. However, their performance degrades

with process variation [3].

In portable system designs, a low-voltage operation plays one

of the key design factors. The voltage limitations of this tech-

nology dictate that the ADC operates at the same low voltage

as the digital circuitry. In the literature, many low-voltage

CMOS ADC integrated circuits have been proposed [5], [6].

However, most of them are more complex circuit designs or

require higher power consumption. Consequently, they are not

suitable for portable system designs.

Manuscript received April 3, 2002; revised August 5, 2002. This work was

supported in part by the Chip Implementation Center, National Science Council

and by the Program of Promoting Academic Excellence, Ministry of Education,

under Grant EX-91-E-FA09-5-4, Taiwan, R.O.C.

The authors are with the Department of Electrical Engineering, Na-

tional Cheng Kung University, Tainan 70101, Taiwan, R.O.C. (e-mail:

bdliu@cad.ee.ncku.edu.tw).

Digital Object Identifier 10.1109/JSSC.2002.806257

Fig. 1. Circuit diagram of a general successive approximation ADC.

In this paper, a novel circuit for low-power low-cost 6-bit

CMOS ADC is presented. A basic successive approximation

ADC (SA-ADC) will first be introduced and followed by an im-

proved successive approximation ADC (ISA-ADC) with stan-

dard CMOS technology. Based on the ISA-ADC architecture, a

parallel-like ISA-ADC architecture for high-speed low-resolu-

tion applications is developed.In addition, the adjustable feature

of the proposed circuit for scaling down the operating voltage

will be shown. The proposed converter has a simple hardware

design and low-accuracy comparator and therefore, is suitable

for low-power low-cost standard CMOS technology VLSI im-

plementation.

II. B

ASIC ARCHITECTURES OF SUCCESSIVE

APPROXIMATION ADC

The architecture of a general SA-ADC usually consists of

a rail-to-rail analog comparator, a digital-to-analog converter

(DAC)andasuccessiveapproximationregister (SAR), as shown

in Fig. 1 [7]. In general, the SAR is designed into the digital

circuitry. The DAC required in the ADC is designed based on

a R-2R ladder. Thus, both of them are suitable for the stan-

dard CMOS technology VLSI implementation. However, real-

izing a high-speed, high-accuracy and rail-to-rail MOS com-

parator concurrently remains a problem because of MOS device

mismatches [8], [9] and threshold voltage limitations [10]. The

input signals of this comparator is expressed by

(1)

where both

and are the comparator inputs and denotes

the comparator operation. This high-speed, offset compensated

and rail-to-rail comparator plays one of the key components for

SA-ADC designs.

To solve this problem, another SA-ADC architecture was de-

veloped to simplify the comparator requirement, as shown in

Fig. 2 [11]. This architecture employs an additional analog sub-

tracter to generate the differential value between the

signal

and the

signal, this way a comparator based on this archi-

tecture is applicable to compare the differential voltage level

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