Philips 89C51RB2/RC2/RD2 微控制器英文原版资料

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"89C51系列是Philips Semiconductors（现为NXP Semiconductors）推出的一款8位微控制器家族，主要型号包括89C51RB2、89C51RC2和89C51RD2。这些设备内置了16KB、32KB或64KB的ISP/IAP Flash程序存储器，以及512B到1KB的RAM。这些微控制器的特点是支持并行编程和串行的In-System Programming (ISP)以及In-Application Programming (IAP)功能。ISP允许用户在微控制器处于应用状态时下载新代码，而IAP则意味着微控制器可以在系统运行中自我更新程序。此外，ROM中预装的串行加载器（bootloader）程序可以通过UART接口无须额外加载器就能对Flash内存进行串行ISP。对于IAP，用户可以擦除并重新编程特定的程序区域，实现了远程通过调制解调器链接进行更新的能力。" 这篇资料详细介绍了89C51系列微控制器的主要特性和规格。89C51是基于80C51架构的，这是一个广泛使用的8位微处理器核心。该系列芯片集成了不同容量的非易失性Flash存储器，可以用于存储程序代码，并且具有ISP和IAP特性，极大地增强了其在实际应用中的灵活性和可升级性。 ISP功能使得用户无需将微控制器从电路板上移除就能更新固件，这对于产品维护和升级非常方便。IAP功能更进一步，允许微控制器在运行过程中更新自己的代码，这在需要动态更新或者修复错误的场合特别有用。例如，通过远程更新，制造商可以解决现场设备的问题，而无需派遣技术人员进行现场服务。此外，89C51系列还内置了RAM，用于数据处理和临时存储。根据不同的型号，RAM的大小有所不同，提供了一定程度的灵活性以适应不同应用的需求。预装在ROM中的bootloader程序简化了通过UART接口的串行编程过程，使得开发者可以更轻松地实现固件的更新和调试。 89C51系列微控制器因其内置的ISP和IAP功能，以及可选的Flash和RAM容量，成为了广泛应用在嵌入式系统、工业控制、智能家居等领域的理想选择。开发者可以利用这些特性来构建灵活、可扩展并且易于维护的系统。

Philips Semiconductors Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Table 1. Special Function Registers (Continued)

SYMBOL DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

MSB LSB

RESET

VALUE

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00000000B

RCAP2H# Timer 2 Capture High CBH 00H

RCAP2L# Timer 2 Capture Low CAH 00H

SADDR# Slave Address A9H 00H

SADEN# Slave Address Mask B9H 00H

SBUF Serial Data Buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98

SCON* Serial Control 98H

SM0/FE

SM1 SM2 REN TB8 RB8 TI RI 00H

SP Stack Pointer 81H 07H

8F 8E 8D 8C 8B 8A 89 88

TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

CF CE CD CC CB CA C9 C8

T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H

T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE DCEN xxxxxx00B

TH0 Timer High 0 8CH 00H

TH1 Timer High 1 8DH 00H

TH2# Timer High 2 CDH 00H

TL0 Timer Low 0 8AH 00H

TL1 Timer Low 1 8BH 00H

TL2# Timer Low 2 CCH 00H

TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

WDTRST Watchdog Timer Reset A6H

* SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

– Reserved bits.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an

on-chip oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. Minimum and maximum

high and low times specified in the data sheet must be observed.

This device is configured at the factory to operate using 6 clock

periods per machine cycle, referred to in this datasheet as “6 clock

mode”. (This yields performance equivalent to twice that of standard

80C51 family devices). It may be optionally configured on

commercially-available EPROM programming equipment to operate

at 12 clocks per machine cycle, referred to in this datasheet as

“12 clock mode”. Once 12 clock mode has been configured, it

cannot be changed back to 6 clock mode.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator

periods in 12 clock mode), while the oscillator is running. To ensure a

good power-on reset, the RST pin must be high long enough to allow

the oscillator time to start up (normally a few milliseconds) plus two

machine cycles. At power-on, the voltage on V

and RST must

come up at the same time for a proper start-up. Ports 1, 2, and 3 will

asynchronously be driven to their reset condition when a voltage

above V

IH1

(min.) is applied to RESET.

The value on the EA

pin is latched when RST is deasserted and has

no further effect.

Philips Semiconductors Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

LOW POWER MODES

Stop Clock Mode

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows

step-by-step utilization and permits reduced system power

consumption by lowering the clock frequency down to any value. For

lowest power consumption the Power Down mode is suggested.

Idle Mode

In the idle mode (see Table 2), the CPU puts itself to sleep while all

of the on-chip peripherals stay active. The instruction to invoke the

idle mode is the last instruction executed in the normal operating

mode before the idle mode is activated. The CPU contents, the

on-chip RAM, and all of the special function registers remain intact

during this mode. The idle mode can be terminated either by any

enabled interrupt (at which time the process is picked up at the

interrupt service routine and continued), or by a hardware reset

which starts the processor in the same manner as a power-on reset.

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

their values down to 2.0 V and care must be taken to return V

the minimum specified operating voltages before the Power Down

Mode is terminated.

Either a hardware reset or external interrupt can be used to exit from

Power Down. Reset redefines all the SFRs but does not change the

on-chip RAM. An external interrupt allows both the SFRs and the

on-chip RAM to retain their values.

To properly terminate Power Down, the reset or external interrupt

should not be executed before V

is restored to its normal

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10 ms).

With an external interrupt, INT0 and INT1 must be enabled and

configured as level-sensitive. Holding the pin low restarts the oscillator

but bringing the pin back high completes the exit. Once the interrupt

is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put the device into Power Down.

POWER OFF FLAG

The Power Off Flag (POF) is set by on-chip circuitry when the V

level on the 89C51RB2/RC2/RD2 rises from 0 to 5 V. The POF bit

can be set or cleared by software allowing a user to determine if the

reset is the result of a power-on or a warm start after powerdown.

The V

level must remain above 3 V for the POF to remain

unaffected by the V

level.

Design Consideration

•When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate the

possibility of an unexpected write when Idle is terminated by reset,

the instruction following the one that invokes Idle should not be

one that writes to a port pin or to external memory.

ONCE Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems without the device having to be removed from

the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN

is high;

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN

are weakly pulled

high. The oscillator circuit remains active. While the device is in this

mode, an emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is applied.

Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0.

This pin, besides being a regular I/O pin, has two alternate

functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at

a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode).

To configure the Timer/Counter 2 as a clock generator, bit C/T

2 (in

T2CON) must be cleared and bit T20E in T2MOD must be set. Bit

TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and

the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)

as shown in this equation:

Oscillator Frequency

n (65536 * RCAP2H, RCAP2L)

n = 2 in 6 clock mode

4 in 12 clock mode

Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L

taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an

interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock

generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

Table 2. External Pin Status During Idle and Power-Down Mode

MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

Philips Semiconductors Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an

event timer or an event counter, as selected by C/T

2* in the special

function register T2CON (see Figure 1). Timer 2 has three operating

modes: Capture, Auto-reload (up or down counting), and Baud Rate

Generator, which are selected by bits in the T2CON as shown in

Table 3.

Capture Mode

In the capture mode there are two options which are selected by bit

EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or

counter (as selected by C/T

2* in T2CON) which, upon overflowing

sets bit TF2, the timer 2 overflow bit. This bit can be used to

generate an interrupt (by enabling the Timer 2 interrupt bit in the

IE register). If EXEN2= 1, Timer 2 operates as described above, but

with the added feature that a 1- to -0 transition at external input

T2EX causes the current value in the Timer 2 registers, TL2 and

TH2, to be captured into registers RCAP2L and RCAP2H,

respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set, and EXF2 like TF2 can generate an interrupt

(which vectors to the same location as Timer 2 overflow interrupt.

The Timer 2 interrupt service routine can interrogate TF2 and EXF2

to determine which event caused the interrupt). The capture mode is

illustrated in Figure 2 (There is no reload value for TL2 and TH2 in

this mode. Even when a capture event occurs from T2EX, the

counter keeps on counting T2EX pin transitions or osc/6 pulses

(osc/12 in 12 clock mode).).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured (as either

a timer or counter [C/T

2* in T2CON]) then programmed to count up

or down. The counting direction is determined by bit DCEN (Down

Counter Enable) which is located in the T2MOD register (see

Figure 3). When reset is applied the DCEN=0 which means Timer 2

will default to counting up. If DCEN bit is set, Timer 2 can count up

or down depending on the value of the T2EX pin.

Figure 4 shows Timer 2 which will count up automatically since

DCEN=0. In this mode there are two options selected by bit EXEN2

in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH

and sets the TF2 (Overflow Flag) bit upon overflow. This causes the

Timer 2 registers to be reloaded with the 16-bit value in RCAP2L

and RCAP2H. The values in RCAP2L and RCAP2H are preset by

software means.

If EXEN2=1, then a 16-bit reload can be triggered either by an

overflow or by a 1-to-0 transition at input T2EX. This transition also

sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be

generated when either TF2 or EXF2 are 1.

In Figure 5 DCEN=1 which enables Timer 2 to count up or down.

This mode allows pin T2EX to control the direction of count. When a

logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will

overflow at 0FFFFH and set the TF2 flag, which can then generate

an interrupt, if the interrupt is enabled. This timer overflow also

causes the 16-bit value in RCAP2L and RCAP2H to be reloaded

into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count

down. The timer will underflow when TL2 and TH2 become equal to

the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets

the TF2 flag and causes 0FFFFH to be reloaded into the timer

registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows.

This EXF2 bit can be used as a 17th bit of resolution if needed. The

EXF2 flag does not generate an interrupt in this mode of operation.

(MSB) (LSB)

Symbol Position Name and Significance

TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

when either RCLK or TCLK = 1.

EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2

interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down

counter mode (DCEN = 1).

RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to

ignore events at T2EX.

TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

T2CON.1 Timer or counter select. (Timer 2)

0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 in 12 clock mode)

1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload

on Timer 2 overflow.

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

CP/RL2

SU01251

Figure 1. Timer/Counter 2 (T2CON) Control Register

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