MT46V32M16 DDR SDRAM：2.5V高速内存，4GB容量与特性概述

需积分: 35 189 浏览量更新于2024-07-17 收藏 2.47MB PDF 举报

本文档主要介绍了Micron Technology公司生产的MT46V32M16 DDR SDRAM芯片的详细规格和特性。DDR SDRAM是一种双倍数据速率（Double Data Rate）动态随机存取存储器，它在每个时钟周期内完成两次数据访问，提高了数据传输效率。首先，MT46V32M16芯片提供了三种不同的容量配置：32兆字节（8 Megabytes），每片具有16个内部银行，支持并行操作，能够同时处理多个读写请求，增强了性能和可靠性。它的工作电压范围为VDD = +2.5V ±0.2V，VDDQ = +2.5V ±0.2V，符合标准的电源要求。数据传输采用双向数据选通（DQS）信号，与数据一起发送和接收，对于x16配置，有两个DQS信号，一个用于每字节的数据捕获，确保了源同步数据传输。该内存采用内置的、带流水线的DDR架构，使得数据读取（READ）时DQS与数据边缘对齐，而写入（WRITE）时DQS与数据中心对齐，这有助于优化时序控制。该芯片还包括一个 DLL（差分延迟锁相环），用于确保DQ（数据线）和DQS信号的转换与时钟信号CK的相位同步。此外，MT46V32M16支持可编程的突发长度，可以选择2、4或8个周期，以便灵活地管理连续的数据读取操作。为了提高可靠性，MT46V32M16采用了更长引脚的TSOP封装（Optically Coupled Leadless Package，无引线光学耦合封装），称为OCPL，这有助于减少信号噪声和提高信号完整性。此外，还支持自动预充电（Auto Precharge）功能，以及自动刷新（Auto Refresh）和自休眠模式（Self Refresh），以延长电池寿命并降低功耗。值得注意的是，此文档提供的信息仅用于评估和参考目的，且可能随时根据Micron Technology的更改而更新。产品本身仅受制于制造商的数据表规格，而非本文档中的讨论。欲获取最新规格，请访问Micron Semi官网（www.micronsemi.com/datasheets/ddrsdramds.html）查询MT46V32M16的最新数据表修订版。 MT46V32M16 DDR SDRAM是一个高性能的存储解决方案，适用于需要高速数据传输和多任务并发处理的应用，其精密设计和灵活的特性使其在现代电子系统中占据重要地位。

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

Figure 3

Extended Mode Register Definition

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these

additional functions are DLL enable/disable and

output drive strength. These functions are controlled

via the bits shown in Figure 3. The extended mode

TER command to the mode register (with BA0 = 1 and

BA1 = 0) and will retain the stored information until it

is programmed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiating

any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are speci-

fied to be SSTL2, Class II. The x16 supports an option

for reduced drive. This option is intended for the

support of the lighter load and/or point-to-point

environments. The selection of the reduced drive

strength will alter the DQs and DQSs from SSTL2, Class

II drive strength to a reduced drive strength, which is

approximately 54% of the SSTL2, Class II drive strength.

Micron will support these x16 options: 1) Full drive

strength only (not programmable), 2) Reduced drive

strength only (not programable), and 3) Program-

mable full or reduced drive strength.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued.

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A6 A5 A4

Extended Mode

Address Bus

654

Drive Strength

Normal

Reduced

–

QFC Function

Disabled

Reserved

E1,

Operating Mode

A10

A11A12

BA0

BA1

1314

NOTE: 1. E14 and E13 (BA0 and BA1) must be “1, 0” to select the

Extended Mode Register (vs. the base Mode Register).

2. The reduced drive strength option is not supported on

the x4 and x8 versions: and is only available on the D3 version

of the x16 device.

3. The QFC# option is not supported.

E2,E3E4

–

E7E8E9

–

E10E11

–

E12

DSQFC

元器件交易网www.cecb2b.com

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

appear following the Operation section; these tables

provide current state/next state information.

COMMANDS

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a verbal descrip-

tion of each command. Two additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-

code to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 9 for x16, 9,11 for x8, and 9, 11, 12 for x4);

A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select bank and activate row) L L H H Bank/Row 3

READ (Select bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER L L L L Op-Code 2

TRUTH TABLE 1A – DM OPERATION

(Note: 10)

NAME (FUNCTION) DM DQs NOTES

Write Enable L Valid

Write Inhibit HX

元器件交易网www.cecb2b.com

512Mb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16

DDR SDRAM

ADVANCE

DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR SDRAM.

The DDR SDRAM is effectively deselected. Operations

already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR SDRAM to perform a NOP

(CS# LOW). This prevents unwanted commands from

being registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0–A12.

See mode register descriptions in the Register Defini-

tion section. The LOAD MODE REGISTER command

can only be issued when all banks are idle, and a

subsequent executable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the

address provided on inputs A0–A12 selects the row.

This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank.

A PRECHARGE command must be issued before open-

ing a different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11,

and 12 for x4) selects the starting column location. The

value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

READ burst; if auto precharge is not selected, the row

will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0–Ai (where i = 9 for x16; 9 and 11 for x8; or 9,

11, and 12 for x4) selects the starting column location.

The value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

WRITE burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array

subject to the DM input logic level appearing coincident

with the data. If a given DM signal is registered LOW, the

corresponding data will be written to memory; if the

DM signal is registered HIGH, the corresponding data

inputs will be ignored, and a WRITE will not be executed

to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all

banks. The bank(s) will be available for a subsequent row

access a specified time (

RP) after the PRECHARGE com-

mand is issued. Input A10 determines whether one or all

banks are to be precharged, and in the case where only

one bank is to be precharged, inputs BA0, BA1 select the

bank. Otherwise BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state

and must be activated prior to any READ or WRITE

commands being issued to that bank. A PRECHARGE

command will be treated as a NOP if there is no open

row in that bank (idle state), or if the previously open

row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the

same individual-bank precharge function described

above, but without requiring an explicit command.

This is accomplished by using A10 to enable auto

precharge in conjunction with a specific READ or

WRITE command. A precharge of the bank/row that is

addressed with the READ or WRITE command is auto-

matically performed upon completion of the READ or

WRITE burst. Auto precharge is nonpersistent in that it

is either enabled or disabled for each individual READ

or WRITE command.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

PRECHARGE command was issued at the earliest pos-

sible time, without violating

RAS (MIN), as described

for each burst type in the Operation section of this data

sheet. The user must not issue another command to the

same bank until the precharge time (

RP) is completed.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate READ bursts (with auto precharge disabled). The

most recently registered READ command prior to the

BURST TERMINATE command will be truncated, as

shown in the Operation section of this data sheet. The

open page which the READ burst was terminated from

remains open.

元器件交易网www.cecb2b.com

剩余69页未读，继续阅读

mypc56

粉丝: 5
资源: 51

MT46V32M16 DDR SDRAM：2.5V高速内存，4GB容量与特性概述

Blackfin平台UBOOT移植步骤与问题解决

Cloudera Manager API v32 教程

SuperDic-V32软件及其安装教程下载指南

MT46V64M4 datasheet

R2V32软件将矢量化图片高效转换为CAD格式

Deep-Learning-with-PyTorch-by-Eli-Stevens-Luca-Antiga-Thomas-Viehmann

直连设备（单片机）端token自动计算（micropython）

基于FPGA的IIR滤波器数字滤波器无限脉冲响应verilog vhdl自适应滤波器实物FIR抽取内插上下变频CIC滤波器 如果需要上述滤波器或者其他滤波器都可以右下角加好友加好友定制 本设计是基于

【Python】Python爬虫实战--小猪短租爬虫_pgj.zip

gym-chrome-dino-master.zip

最新资源

基于FPGA的IIR滤波器数字滤波器无限脉冲响应verilog vhdl自适应滤波器实物FIR抽取内插上下变频CIC滤波器如果需要上述滤波器或者其他滤波器都可以右下角加好友加好友定制本设计是基于