ARM与Thumb-2指令集速查卡片

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"《ARM® and Thumb®-2 Instruction Set Quick Reference Card》是国外网友整理的一份关于ARM和Thumb-2指令集的速记卡片，旨在帮助学习者更有效地记忆和理解ARM指令集。这份卡片适合打印出来作为学习辅助工具，方便随时查阅和复习。" 在ARM架构中，指令集是其核心组成部分，它定义了处理器能够执行的操作。ARM和Thumb-2是ARM架构中的两种主要指令集，分别针对不同的应用需求。ARM指令集通常用于提供高性能的处理能力，而Thumb-2指令集则以其紧凑的编码空间和接近ARM指令集的性能而闻名，适用于资源受限的环境。速记卡片中的关键信息包括： 1. **Rm{,<opsh>}**：表示一个寄存器（Rm）可能经过不同类型的位操作（如移位操作，由<opsh>指定）。这允许对数据进行预处理或调整，以适应特定的指令需求。 2. **<reglist>**：是一个用括号{}包围的、逗号分隔的寄存器列表，可以用于指定多个寄存器作为操作数。 3. **<Operand2>**：灵活的第二操作数，可以包含位移和旋转操作，增加了指令的灵活性。 4. **<reglist-PC>** 和 **<reglist+PC>**：与寄存器列表类似，但分别指出是否包含程序计数器（PC）。 5. **<PSR>**：表示程序状态寄存器，包括APSR（应用程序状态寄存器）、CPSR（当前处理器状态寄存器）和SPSR（保存的处理器状态寄存器），它们记录了处理器执行时的状态，如标志位。 6. **<flags>**：指的是ALU（算术逻辑单元）标志或SIMD（单指令多数据）浮点标志，如nzcvq（非零、进位、溢出、校验位和快速）和g（大于）、e（等于）等。 7. **C*, V***：这些标志在早期的ARM架构版本（v4及之前）中可能是不可预测的，但在v5及以后版本中保持不变。 8. **<Rs|sh>**：可以是寄存器Rs或者立即数形式的移位值，根据表中指定的规则进行移位操作。 9. **<iflags>**：中断标志，用于控制处理器对中断的响应，如a（abort），i（interrupt）和f（fast interrupt）。 10. **x, y**：用于表示半寄存器，x代表低16位（[15:0]），y代表高16位（[31:16]），常用于双精度浮点运算。 11. **<p_mode>**：处理器模式，例如用户模式、系统模式、中断模式等，不同的模式决定了哪些寄存器和标志可以访问。这份速记卡片包含了ARM和Thumb-2指令集中的关键概念，对熟悉指令集、编写汇编代码或调试ARM系统的人来说，是非常有价值的参考资料。通过学习和熟记这些内容，开发者可以更高效地利用ARM处理器的能力，实现高效能和低功耗的系统设计。

ARM

and Thumb

-2 Instruction Set

Quick Reference Card

Key to Tables

Rm {, <opsh>} See Table Register, optionally shifted by constant <reglist> A comma-separated list of registers, enclosed in braces { and }.

<Operand2> See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2. <reglist-PC> As <reglist>, must not include the PC.

<fields> See Table PSR fields. <reglist+PC> As <reglist>, including the PC.

<PSR> APSR (Application Program Status Register), CPSR (Current Processor Status Register), or SPSR

(Saved Processor Status Register)

<flags> Either nzcvq (ALU flags PSR[31:27]) or g (SIMD GE flags

PSR[19:16])

C*, V* Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later. § See Table ARM architecture versions.

<Rs|sh> Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those +/- + or –. (+ may be omitted.)

shown in Table Register, optionally shifted by constant. <iflags> Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).

x,y B meaning half-register [15:0], or T meaning [31:16]. <p_mode> See Table Processor Modes

<imm8m> ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. SPm SP for the processor mode specified by <p_mode>

Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit <lsb> Least significant bit of bitfield.

pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00. <width> Width of bitfield. <width> + <lsb> must be <= 32.

<prefix> See Table Prefixes for Parallel instructions {X} RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.

{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before. {!} Updates base register after data transfer if ! present (pre-indexed).

IB and DA are not available in Thumb state. If omitted, defaults to IA. {S} Updates condition flags if S present.

<size> B, SB, H, or SH

, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively. {T} User mode privilege if T present.

SB and SH are not available in STR instructions. {R} Rounds result to nearest if R present, otherwise truncates result.

Operation § Assembler S updates Action Notes

Add Add ADD{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 N

with carry ADC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 + Carry N

wide T2 ADD Rd, Rn, #<imm12> Rd := Rn + imm12, imm12 range 0-4095 T, P

saturating {doubled} 5E Q{D}ADD Rd, Rm, Rn Rd := SAT(Rm + Rn) doubled: Rd := SAT(Rm + SAT(Rn * 2)) Q

Address Form PC-relative address ADR Rd, <label> Rd := <label>, for <label> range from current instruction see Note L N, L

Subtract Subtract SUB{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 N

with carry SBC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 – NOT(Carry) N

wide T2 SUB Rd, Rn, #<imm12> Rd := Rn – imm12, imm12 range 0-4095 T, P

reverse subtract RSB{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn N

reverse subtract with carry RSC{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn – NOT(Carry) A

saturating {doubled} 5E Q{D}SUB Rd, Rm, Rn Rd := SAT(Rm – Rn) doubled: Rd := SAT(Rm – SAT(Rn * 2)) Q

Exception return without stack SUBS PC, LR, #<imm8> N Z C V PC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255.

Parallel

arithmetic

Halfword-wise addition 6 <prefix>ADD16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0] G

Halfword-wise subtraction 6 <prefix>SUB16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0] G

Byte-wise addition 6 <prefix>ADD8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],

Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]

Byte-wise subtraction 6 <prefix>SUB8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],

Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]

Halfword-wise exchange, add, subtract 6 <prefix>ASX Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16] G

Halfword-wise exchange, subtract, add 6 <prefix>SAX Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16] G

Unsigned sum of absolute differences 6 USAD8 Rd, Rm, Rs Rd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

and accumulate 6 USADA8 Rd, Rm, Rs, Rn Rd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

Saturate Signed saturate word, right shift 6 SSAT Rd, #<sat>, Rm{, ASR <sh>} Rd := SignedSat((Rm ASR sh), sat). <sat> range 1-32, <sh> range 1-31. Q, R

Signed saturate word, left shift 6 SSAT Rd, #<sat>, Rm{, LSL <sh>} Rd := SignedSat((Rm LSL sh), sat). <sat>

range 1-32, <sh> range 0-31. Q

Signed saturate two halfwords 6 SSAT16 Rd, #<sat>, Rm Rd[31:16] := SignedSat(Rm[31:16], sat),

Rd[15:0] := SignedSat(Rm[15:0], sat). <sat> range 1-16.

Unsigned saturate word, right shift 6 USAT Rd, #<sat>, Rm{, ASR <sh>} Rd := UnsignedSat((Rm ASR sh), sat). <sat> range 0-31, <sh> range 1-31. Q, R

Unsigned saturate word, left shift 6 USAT Rd, #<sat>, Rm{, LSL <sh>} Rd := UnsignedSat((Rm LSL sh), sat). <sat> range 0-31, <sh> range 0-31. Q

Unsigned saturate two halfwords 6 USAT16 Rd, #<sat>, Rm Rd[31:16] := UnsignedSat(Rm[31:16], sat),

Rd[15:0] := UnsignedSat(Rm[15:0], sat). <sat> range 0-15.

ARM® and Thumb®-2

Instruction Set Quick

Reference Card

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