"M24256E EEPROM芯片资料及特性详解"

芯片资料

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Bit b7:b4 Reserved bits - Read as '0'. (b7,b6,b5,b4)=(0,0,0,0)

Bit b3:b1

C2, C1, C0: Configurable device address bits

b3, b2, b1 are used to configure up to eight possibilities of chip enable address:

• (b3, b2, b1) = (0, 0, 0): the chip enable address is 000 (factory delivery value)

• (b3, b2, b1) = (0, 0, 1): the chip enable address is 001

• (b3, b2, b1) = (0, 1, 0): the chip enable address is 010

• (b3, b2, b1) = (0, 1, 1): the chip enable address is 011

• (b3, b2, b1) = (1, 0, 0): the chip enable address is 100

• (b3, b2, b1) = (1, 0, 1): the chip enable address is 101

• (b3, b2, b1) = (1, 1 0): the chip enable address is 110

• (b3, b2, b1) = (1, 1, 1): the chip enable address is 111

Bit b0

DAL: device address lock bit

b0 locks the CDA regster in read-only mode:

• b0 = 0: bits b3,b2,b1,b0 can be modified

• b0 = 1: bits b3,b2,b1,b0 cannot be modified and therefore the CDA register is frozen

Note: bits b3 to b0 can be updated (if b0 = 0) in the same write instruction. Setting b0 from 0 to 1 is an

irreversible action.

C2, C1, C0 and DAL are defining the chip enable address in the device select code and the device address lock.

These bits can be written and re-configured with a write command.

At power up or after reprogramming, the device load the last configuration of C2, C1, C0 and DAL values.

In order to prevent unwanted change of configurable device address bits, the M24256E proposes to protect the

CDA register,freezing it in read-only mode. The update of the CDA register is disabled (read-only) when the DAL

bit is set to '1' (DAL=1b).

In the same way, the update of the CDA register is enabled when the DAL bit is set to '0' (DAL= 0b).

Note: • Updating the DAL bit from 0 to 1 is an irreversible action: the C2,C1,C0 and DAL bits cannot be updated

any more.

• If the write control input (

WC) is driven high or if the DAL bit is set to 1, the write configurable device

address command is not executed and the accompanying data byte is not acknowledged, as shown in

Figure 7.

M24256E-F

Configurable device address register (CDA)

DS12687 - Rev 2

page 8/46

5.3 Data input

During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct

device operation,serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data

(SDA) signal must change only when serial clock (SCL) is driven low.

5.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master

or slave device, releases serial data (SDA) after sending eight bits of data. During the 9

clock pulse period, the

receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits.

5.5 Device addressing

To start communication between the bus master and the slave device, the bus master must initiate a start

condition. Following this, the bus master sends the device select code and byte address as specified in Table 3,

Table 4 and Table 5.

Table 3. Device address

Features

Device type identifier Chip enable address

Bit 0 (LSB)

Bit 7 (MSB)

(1)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Memory

1 0 1 0 C2 C1 C0

R/W

Identification page 1 0 1 1 C2 C1 C0 R/W

Identification page lock 1 0 1 1 C2 C1 C0 R/W

Configurable device address 1 0 1 1 C2 C1 C0 R/W

1. The most significant bit, b7, is sent first.

Table 4. First word address

Features

Bit 7 (MSB)

(1)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory

(2)

A14 A13 A12 A11 A10 A9 A8

Identification page

(3)

X X 0 X X

Identification page lock

(3)

X X 1 X X

Configurable device address 1 1 0 X X X X X

1. The most significant bit, b7, is sent first.

2. X = Don't care

3. For identification page do not use A15/A14/A13 equal to '110'

Table 5. Second word address

Features

Bit 7 (MSB)

(1)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

Memory A7 A6 A5 A4 A3 A2 A1 A0

Identification page

(2)

X A5 A4 A3 A2 A1 A0

Identification page lock X X X X X X X X

Configurable device address X X X X X X X X

1. The most significant bit, b7, is sent first.

2. X = Don't care

When the device select code is received, the device responds only if the bit 3, bit 2 and bit 1 values match the

values of the C2, C1 and C0 bits programmed in the configurable device address register.

M24256E-F

Data input

DS12687 - Rev 2

page 10/46

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