Intel Arria 10 FPGA 25G Ethernet用户手册

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"该文档是25G Ethernet Intel Arria 10 FPGA IP核心的用户指南，用于指导用户如何在Intel Quartus Prime Design Suite 19.4版本中使用此高性能以太网解决方案。该IP核心支持25Gbps速率，并详细介绍了其特性、设备家族与速度等级支持、验证方法、性能和资源利用率，以及如何开始使用和集成到设计中。" 本文档主要涵盖以下几个关键知识点： 1. **25G Ethernet Intel FPGA IP Core**: 这是一个专为Intel Arria 10 FPGA设计的25千兆以太网接口IP核心，旨在提供高速数据传输能力，适用于数据中心、网络通信等应用。 2. **支持特性**: 25G Ethernet IP核心具备多种功能，包括但不限于符合IEEE 802.3by标准的25 Gigabit Ethernet协议支持、流控制、错误检测和校正机制等。 3. **设备家族和速度等级支持**: 支持Intel Arria 10系列的不同设备家族，且详细列出了各个设备的速度等级，以满足不同应用环境和性能需求。 4. **IP Core验证**: 验证过程包括模拟环境的设置、编译检查和硬件测试，确保IP核心在实际应用中的正确性和可靠性。 5. **性能和资源利用率**: 文档中会提供IP核心在实现25Gbps以太网功能时对FPGA资源的占用情况，包括逻辑元件、内存块和I/O引脚等，帮助用户评估设计的效率和可行性。 6. **开始使用**: 包含安装和授权Intel FPGA IP核心的步骤，以及如何配置IP核心参数和选项，便于用户快速上手。 7. **模拟IP Core**: 用户可以通过仿真工具验证IP核心的功能，确保设计在硬件实现前满足预期。 8. **生成文件结构**: 描述了在设计流程中生成的各类文件及其用途，帮助用户理解设计输出。 9. **设计集成**: 提供了关于引脚分配、添加收发器PLL（锁相环）以及处理可能的抖动问题的指导，确保IP核心能无缝融入用户的设计。 10. **处理潜在抖动**: 在Intel Arria 10器件中，可能会遇到信号质量问题，如抖动，文档提供了相应的处理策略，以维持高数据传输的稳定性。这份用户指南是针对开发人员和工程师的宝贵参考资料，它详细阐述了如何在Intel Arria 10 FPGA平台上实现和优化25G Ethernet功能，对于那些寻求高速网络连接解决方案的人来说至关重要。

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Related Information

• Intel Quartus Prime Licensing Site

• Introduction to Intel FPGA Software Installation and Licensing

2.2. Specifying the 25G Ethernet Intel FPGA IP Core Parameters

and Options

The 25G Ethernet Intel FPGA IP parameter editor allows you to quickly configure your

custom IP variation. Use the following steps to specify IP core options and parameters

in the Intel Quartus Prime software.

1. Depending on whether you are using the Intel Quartus Prime Pro Edition software

or the Intel Quartus Prime Standard Edition software, perform one of the following

actions:

•

In the Intel Quartus Prime Pro Edition, click File ➤ New Project Wizard to

create a new Quartus Prime project, or File ➤ Open Project to open an

existing Quartus Prime project. The wizard prompts you to specify a device.

• In the Intel Quartus Prime Standard Edition software, in the IP Catalog (Tools

➤ IP Catalog), select the Arria 10 target device family.

In the IP Catalog (Tools ➤ IP Catalog), locate and double-click the name of the

IP core to customize. The New IP Variation window appears.

3. In the New IP Variation dialog box, specify a top-level name for your custom IP

variation. The parameter editor saves the IP variation settings in a file named

<your_ip>.qsys (in Intel Quartus Prime Standard Edition) or <your_ip>.ip (in

Intel Quartus Prime Pro Edition).

4. In the Intel Quartus Prime Standard Edition software, you must select a specific

Intel Arria 10 device in the Device field, or keep the default device the Quartus

Prime software proposes.

5. Click OK. The parameter editor appears.

6. On the IP tab, specify the parameters for your IP core variation. Refer to 25G

Ethernet Intel FPGA IP Core Parameters on page 24 for information about specific

IP core parameters.

7. Optionally, to generate a simulation testbench or compilation and hardware design

example, follow the instructions in the Intel Arria 10 25G Ethernet Design Example

User Guide.

8. Click Generate HDL. The Generation dialog box appears.

9. Specify output file generation options, and then click Generate. The IP variation

files generate according to your specifications.

Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your

IP core variation.

10.

Click Finish. The parameter editor adds the top-level .qsys or .ip file to the

current project automatically. If you are prompted to manually add the .qsys

or .ip file to the project, click Project ➤ Add/Remove Files in Project to add

the file.

11. After generating and instantiating your IP variation, make appropriate pin

assignments to connect ports.

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Related Information

Intel Arria 10 25G Ethernet Design Example User Guide

Information about the Example Design tab in the 25G Ethernet Intel FPGA IP

parameter editor.

2.3. Simulating the IP Core

You can simulate your 25G Ethernet Intel FPGA IP core variation with the functional

simulation model and the testbench generated with the IP core. The functional

simulation model is a cycle-accurate model that allows for fast functional simulation of

your IP core instance using industry-standard Verilog HDL simulators. You can

simulate the Intel-provided testbench or create your own testbench to exercise the IP

core functional simulation model.

The functional simulation model and testbench files are generated in project

subdirectories. These directories also include scripts to compile and run the design

example.

Note: Use the simulation models only for simulation and not for synthesis or any other

purposes. Using these models for synthesis creates a nonfunctional design.

In the top-level wrapper file for your simulation project, you can set the the following

RTL parameters to enable simulation optimization. These optimizations significantly

decrease the time to reach link initialization.

• SIM_SHORT_RST: Shortens the reset times to speed up simulation.

• SIM_SHORT_AM: Shortens the interval between alignment markers to accelerate

alignment marker lock. Alignment markers are used when Reed-Solomon FEC is

enabled.

•

SIM_SIMPLE_RATE: Sets the PLL reference clock (clk_ref) to 625 MHz instead of

644.53125 MHz to optimize PLL simulation model behavior

In general, parameters are set through the IP core parameter editor and you should

not change them manually. The only exceptions are these simulation optimization

parameters.

To set these parameters on the PHY blocks, add the following lines to the top-level

wrapper file:

defparam <dut instance>.SIM_SHORT_RST = 1'b1;

defparam <dut instance>.SIM_SHORT_AM = 1'b1;

defparam <dut instance>.SIM_SIMPLE_RATE = 1'b1;

Note: You can use the example testbench as a guide for setting the simulation parameters in

your own simulation environment. These lines are already present in the Intel-

provided testbench for the IP core.

Related Information

• Simulating Intel FPGA Designs

Quartus Prime Standard Edition Handbook Volume 3: Verification chapter that

provides information about simulating Intel FPGA IP cores.

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• Intel Arria 10 25G Ethernet Design Example User Guide

Information about generating and simulating the Intel-provided 25G Ethernet

Intel FPGA IP testbench. This testbench demonstrates a basic test of the IP

core. It is not intended to be a substitute for a full verification environment.

2.4. Generated File Structure

The Intel Quartus Prime software generates the following IP core output file structure.

For information about the file structure of the design example, refer to the Arria 10

25G Ethernet Intel FPGA IP Design Example User Guide.

Figure 5. IP Core Generated Files

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file

<your_ip>.qip - Lists IP synthesis files

<your_ip>.sip - Lists files for simulation

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd

Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys or .ip - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report

<your_ip>.debuginfo - Contains post-generation information (Standard Edition only)

<your_ip>.html - Connection and memory map data

<your_ip>.bsf - Block symbol schematic

<your_ip>.spd - Combines individual simulation scripts

<your_ip>.sopcinfo - Software tool-chain integration file

(Standard Edition only)

<your_ip>

IP variation files

alt_e25_0_example_design

Example location for your IP core

design example files. The default location is

alt_e25_0_example_design, but

you are prompted to specify a different path

sim

Simulation files

synth

IP synthesis files

Simulator scripts

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip>_<n>

IP variation files

<your_ip>.qgsynthc - Lists synthesis parameters to support incremental regeneration (Pro Edition only)

<your_ip>.qgsimc - Lists simulation parameters to support incremental regeneration (Pro Edition only)

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Table 8. IP Core Generated Files

File Name Description

<your_ip>.qsys (Intel Quartus Prime

Standard Edition only)

The Platform Designer system or top-level IP variation file. <your_ip> is the

name that you give your IP variation.

<your_ip>.ip (Intel Quartus Prime Pro

Edition only)

<system>.sopcinfo

Describes the connections and IP component parameterizations in your

Platform Designer system. You can parse its contents to get requirements

when you develop software drivers for IP components. (Intel Quartus Prime

Standard Edition only)

Downstream tools such as the Nios

II Gen 2 tool chain use this file.

The .sopcinfo file and the system.h file generated for the Nios II Gen 2 tool

chain include address map information for each slave relative to each master

that accesses the slave. Different masters may have a different address map to

access a particular slave component.

<your_ip>.cmp

The VHDL Component Declaration (.cmp) file is a text file that contains local

generic and port definitions that you can use in VHDL design files.

This IP core does not support VHDL. However, the Intel Quartus Prime software

generates this file.

<your_ip>.html

A report that contains connection information, a memory map showing the

address of each slave with respect to each master to which it is connected, and

parameter assignments.

<your_ip>_generation.rpt

IP or Platform Designer generation log file. A summary of the messages during

IP generation.

<your_ip>.debuginfo

Contains post-generation information. Used to pass System Console and Bus

Analyzer Toolkit information about the Platform Designer interconnect. The Bus

Analysis Toolkit uses this file to identify debug components in the Platform

Designer interconnect. (Intel Quartus Prime Standard Edition only)

<your_ip>.qgsimc

Lists simulation parameters to support incremental regeneration. (Intel

Quartus Prime Pro Edition only)

<your_ip>.qgsynthc

Lists synthesis parameters to support incremental regeneration. (Intel Quartus

Prime Pro Edition only)

<your_ip>.qip

Contains all the required information about the IP component to integrate and

compile the IP component in the Intel Quartus Prime software.

<your_ip>.csv

Contains information about the upgrade status of the IP component.

<your_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Intel

Quartus Prime Block Diagram Files (.bdf).

<your_ip>.spd Required input file for ip-make-simscript to generate simulation scripts for

supported simulators. The .spd file contains a list of files generated for

simulation, along with information about memories that you can initialize.

<your_ip>.ppf

The Pin Planner File (.ppf) stores the port and node assignments for IP

components created for use with the Pin Planner.

<your_ip>_bb.v

You can use the Verilog black-box (_bb.v) file as an empty module declaration

for use as a black box.

<your_ip>.sip

Contains information required for NativeLink simulation of IP components. You

must add the .sip file to your Quartus Prime project. (Intel Quartus Prime

Standard Edition only)

<your_ip>_inst.v and _inst.vhd

HDL example instantiation template. You can copy and paste the contents of

this file into your HDL file to instantiate the IP variation.

This IP core does not support VHDL. However, the Intel Quartus Prime software

generates the _inst.vhd file.

continued...

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File Name Description

<your_ip>.regmap

If IP contains register information, .regmap file generates. The .regmap file

describes the register map information of master and slave interfaces. This file

complements the .sopcinfo file by providing more detailed register information

about the system. This enables register display views and user customizable

statistics in the System Console.

<your_ip>.svd

Allows hard processor system (HPS) System Debug tools to view the register

maps of peripherals connected to HPS within a Platform Designer system.

During synthesis, the .svd files for slave interfaces visible to System Console

masters are stored in the .sof file in the debug section. System Console reads

this section, which Platform Designer can query for register map information.

For system slaves, Platform Designer can access the registers by name.

<your_ip>.v

and

<your_ip>.vhd

HDL files that instantiate each submodule or child IP core for synthesis or

simulation.

This IP core does not support VHDL. However, the Intel Quartus Prime software

generates this file.

mentor/ Contains a ModelSim script msim_setup.tcl to set up and run a simulation.

aldec/ Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a

simulation.

synopsys/vcs/

synopsys/vcsmx/

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX

simulation.

cadence/ Contains a shell script ncsim_setup.sh and other setup files to set up and

run an NCSIM simulation.

submodules/

Contains HDL files for the IP core submodule.

<child IP cores>/

For each generated child IP core directory, Platform Designer generates

synth/ andsim/ sub-directories.

Related Information

Intel Arria 10 25G Ethernet Design Example User Guide

Information about the 25G Ethernet Intel FPGA IP design example file structure.

2.5. Integrating Your IP Core in Your Design

2.5.1. Pin Assignments

When you integrate your 25G Ethernet Intel FPGA IP core instance in your design, you

must make appropriate pin assignments. While compiling the IP core alone, you can

create virtual pins to avoid making specific pin assignments for top-level signals.

When you are ready to map the design to hardware, you can change to the correct pin

assignments.

Related Information

Intel Quartus Prime Help

For information about the Intel Quartus Prime software, including virtual pins.

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